Searched refs:ShiftBits (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 563 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() local
566 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
650 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore() local
655 .addImm(ShiftBits ? 32 - ShiftBits : 0) in lowerCRBitRestore()
656 .addImm(ShiftBits) in lowerCRBitRestore()
657 .addImm(ShiftBits); in lowerCRBitRestore()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 405 unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4; in StoreRegToStackSlot() local
408 .addReg(ScratchReg).addImm(ShiftBits) in StoreRegToStackSlot()
540 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; in LoadRegFromStackSlot() local
543 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0) in LoadRegFromStackSlot()
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| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| D | BasicAliasAnalysis.cpp | 372 if (unsigned ShiftBits = 64-TD->getPointerSizeInBits()) { in DecomposeGEPExpression() local
373 Scale <<= ShiftBits; in DecomposeGEPExpression()
374 Scale = (int64_t)Scale >> ShiftBits; in DecomposeGEPExpression()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1863 unsigned ShiftBits = AndRHSC.countTrailingZeros(); in SimplifySetCC() local
1870 DAG.getConstant(ShiftBits, dl, in SimplifySetCC()
1872 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy); in SimplifySetCC()
1883 unsigned ShiftBits; in SimplifySetCC() local
1887 ShiftBits = C1.countTrailingOnes(); in SimplifySetCC()
1891 ShiftBits = C1.countTrailingZeros(); in SimplifySetCC()
1893 NewC = NewC.lshr(ShiftBits); in SimplifySetCC()
1894 if (ShiftBits && NewC.getMinSignedBits() <= 64 && in SimplifySetCC()
1902 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
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| D | DAGCombiner.cpp | 2969 unsigned ShiftBits = CShift->getZExtValue(); in visitANDLike() local
2976 (ShiftBits + MaskBits <= Size / 2) && in visitANDLike()
2988 assert(ShiftBits != 0 && MaskBits <= Size); in visitANDLike()
2996 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT); in visitANDLike()
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| /external/llvm/lib/Analysis/ |
| D | BasicAliasAnalysis.cpp | 329 unsigned ShiftBits = 64 - PointerSize; in adjustToPointerSize() local
330 return (int64_t)((uint64_t)Offset << ShiftBits) >> ShiftBits; in adjustToPointerSize()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4604 SDValue ShiftBits = DAG.getConstant(IdxVal, dl, MVT::i8); in insert1BitVector() local
4605 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, WideSubVec, ShiftBits); in insert1BitVector()
4623 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8); in insert1BitVector() local
4625 Vec = DAG.getNode(X86ISD::VSRLI, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
4626 Vec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
4640 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8); in insert1BitVector() local
4642 Vec = DAG.getNode(X86ISD::VSHLI, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
4643 Vec = DAG.getNode(X86ISD::VSRLI, dl, WideOpVT, Vec, ShiftBits); in insert1BitVector()
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