Searched refs:ShiftOpcode (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCompares.cpp | 1694 unsigned ShiftOpcode = Shift->getOpcode(); in visitICmpInstWithInstAndIntCst() local
1695 if (ShiftOpcode == Instruction::AShr) { in visitICmpInstWithInstAndIntCst()
1699 } else if (ShiftOpcode == Instruction::Shl) { in visitICmpInstWithInstAndIntCst()
1707 } else if (ShiftOpcode == Instruction::LShr) { in visitICmpInstWithInstAndIntCst()
1728 if (ShiftOpcode == Instruction::Shl) in visitICmpInstWithInstAndIntCst()
1735 if (ConstantExpr::get(ShiftOpcode, NewCst, ShAmt) != RHS) { in visitICmpInstWithInstAndIntCst()
1746 if (ShiftOpcode == Instruction::Shl) in visitICmpInstWithInstAndIntCst()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1671 constexpr IValueT ShiftOpcode = B3 | B2 | B0; // 1101 in emitShift() local
1687 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, in emitShift()
1702 emitType01(Cond, kInstTypeDataRegShift, ShiftOpcode, SetFlags, Rn, Rd, in emitShift()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20230 unsigned ShiftOpcode = Op->getOpcode(); in LowerShift() local
20260 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT)); in LowerShift()
20267 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT)); in LowerShift()
20274 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT)); in LowerShift()
20293 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo, in LowerShift()
20295 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi, in LowerShift()
20305 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo, in LowerShift()
20307 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi, in LowerShift()
20317 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo, in LowerShift()
20319 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi, in LowerShift()
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