| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 343 ARM_AM::ShiftOpc ShiftTy; member
352 ARM_AM::ShiftOpc ShiftTy; member
358 ARM_AM::ShiftOpc ShiftTy; member
675 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
720 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
974 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
982 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); in addRegShiftedImmOperands()
1409 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
1511 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
1525 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
[all …]
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 525 ARM_AM::ShiftOpc ShiftTy; member
535 ARM_AM::ShiftOpc ShiftTy; member
542 ARM_AM::ShiftOpc ShiftTy; member
1088 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1209 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1819 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); in addRegShiftedImmOperands()
2423 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
2653 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
2666 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1831 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1840 ShiftTy))); in SimplifySetCC()
1849 ShiftTy))); in SimplifySetCC()
1865 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1871 ShiftTy)); in SimplifySetCC()
1897 EVT ShiftTy = DCI.isBeforeLegalize() in SimplifySetCC() local
1902 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
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| D | LegalizeIntegerTypes.cpp | 2363 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
2364 assert(ShiftTy.getScalarType().getSizeInBits() >= in ExpandIntRes_Shift()
2367 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2368 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
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| D | SelectionDAGBuilder.cpp | 2637 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
2641 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2642 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift()
2648 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2655 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 797 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); in genConstMult()
822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 156 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2747 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2790 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2793 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2308 EVT ShiftTy = DCI.isBeforeLegalize() ? in SimplifySetCC() local
2315 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); in SimplifySetCC()
2323 DAG.getConstant(C1.logBase2(), ShiftTy))); in SimplifySetCC()
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| D | SelectionDAGBuilder.cpp | 2562 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); in visitShift() local
2565 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2566 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift()
2572 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2579 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 28563 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
28564 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
28569 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1) in foldXorTruncShiftIntoCmp()
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