| /external/pdfium/third_party/base/numerics/ |
| D | safe_math_impl.h | 309 using ShiftType = typename std::make_unsigned<T>::type;
310 static const ShiftType kBitWidth = IntegerBitsPlusSign<T>::value;
311 const ShiftType real_shift = static_cast<ShiftType>(shift);
339 using ShiftType = typename std::make_unsigned<T>::type;
340 if (static_cast<ShiftType>(shift) < IntegerBitsPlusSign<T>::value) {
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 1048 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 }; enum
1053 Shift(ShiftType shift) : shift_(shift) {} // NOLINT(runtime/explicit) in Shift()
1054 explicit Shift(uint32_t shift) : shift_(static_cast<ShiftType>(shift)) {} in Shift()
1056 ShiftType GetType() const { return shift_; } in GetType()
1070 void SetType(ShiftType s) { shift_ = s; } in SetType()
1073 ShiftType shift_;
1129 RegisterShiftOperand(ShiftType shift, Register shift_register) in RegisterShiftOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg member
708 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
740 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
746 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
761 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
763 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
771 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1176 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
1326 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
[all …]
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| /external/vixl/test/aarch32/ |
| D | test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 141 ShiftType ror;
726 ShiftType ror = kTests[i].operands.ror; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 141 ShiftType ror;
726 ShiftType ror = kTests[i].operands.ror; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 143 ShiftType shift;
1030 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 143 ShiftType shift;
1020 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 143 ShiftType shift;
1030 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 143 ShiftType shift;
1020 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc | 142 ShiftType ror;
1133 ShiftType ror = kTests[i].operands.ror; in TestHelper()
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| D | test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 68 ShiftType shift;
378 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc | 142 ShiftType ror;
1133 ShiftType ror = kTests[i].operands.ror; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 156 ShiftType shift;
1451 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 156 ShiftType shift;
1451 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 156 ShiftType shift;
1461 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-rs-t32.cc | 137 ShiftType shift;
1711 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 156 ShiftType shift;
1461 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 143 ShiftType shift;
1723 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 76 ShiftType shift;
841 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc | 68 ShiftType shift;
622 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 76 ShiftType shift;
813 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 156 ShiftType shift;
2156 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 89 ShiftType shift;
2663 ShiftType shift = kTests[i].operands.shift; in TestHelper()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 169 AArch64_AM::ShiftExtendType ShiftType,
201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
1200 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend; in emitAddSub() local
1203 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break; in emitAddSub()
1204 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break; in emitAddSub()
1205 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break; in emitAddSub()
1208 if (ShiftType != AArch64_AM::InvalidShiftExtend) { in emitAddSub()
1214 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1317 AArch64_AM::ShiftExtendType ShiftType, in emitAddSub_rs() argument
1351 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
[all …]
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg member
1195 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1248 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1254 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1269 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1271 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1279 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2131 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
2340 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
[all …]
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