| /external/python/cpython2/Doc/library/ |
| D | curses.rst | 1389 | ``KEY_SBEG`` | Shifted Beg (beginning) |
1391 | ``KEY_SCANCEL`` | Shifted Cancel |
1393 | ``KEY_SCOMMAND`` | Shifted Command |
1395 | ``KEY_SCOPY`` | Shifted Copy |
1397 | ``KEY_SCREATE`` | Shifted Create |
1399 | ``KEY_SDC`` | Shifted Delete char |
1401 | ``KEY_SDL`` | Shifted Delete line |
1405 | ``KEY_SEND`` | Shifted End |
1407 | ``KEY_SEOL`` | Shifted Clear line |
1409 | ``KEY_SEXIT`` | Shifted Dxit |
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64Schedule.td | 26 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
29 def ReadISReg : SchedRead; // ALU of Shifted-Reg
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| D | AArch64SchedA57.td | 138 // Shifted Register with Shift == 0
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1792 unsigned Shifted = 0; in alignToARMConstant() local
1799 Shifted += 2; in alignToARMConstant()
1808 if (Shifted > 24) in alignToARMConstant()
1809 Value = Value >> (Shifted - 24); in alignToARMConstant()
1811 Value = Value << (24 - Shifted); in alignToARMConstant()
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| D | ARMInstrThumb2.td | 43 // Shifted operands. No register controlled shifts for Thumb2.
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2498 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, in LowerBUILD_VECTOR() local
2518 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); in LowerBUILD_VECTOR()
2649 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, in LowerEXTRACT_VECTOR() local
2651 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); in LowerEXTRACT_VECTOR()
2697 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width, in LowerINSERT_VECTOR() local
2699 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset); in LowerINSERT_VECTOR()
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| /external/llvm/lib/Target/PowerPC/ |
| D | p9-instrs.txt | 11 // Add PC Immediate Shifted DX-form p69
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| /external/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 4038 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); in createAddRecFromPHI() local
4039 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this); in createAddRecFromPHI()
4040 if (Shifted != getCouldNotCompute() && in createAddRecFromPHI()
4048 ValueExprMap[SCEVCallbackVH(PN, this)] = Shifted; in createAddRecFromPHI()
4049 return Shifted; in createAddRecFromPHI()
8799 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
8801 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /external/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 4973 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); in SwitchToLookupTable() local
4975 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit"); in SwitchToLookupTable()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 85 # Vector Move Immediate Shifted
86 # Vector Move Inverted Immediate Shifted
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| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| D | ScalarEvolution.cpp | 6209 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
6212 dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 370 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
3995 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, in MatchRotatePosNeg() argument
4006 EVT VT = Shifted.getValueType(); in MatchRotatePosNeg()
4009 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, in MatchRotatePosNeg()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 43 // Shifted operands. No register controlled shifts for Thumb2.
|