Home
last modified time | relevance | path

Searched refs:Spill (Results 1 – 25 of 75) sorted by relevance

123

/external/llvm/test/CodeGen/X86/
Davx-intel-ocl.ll70 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
71 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
72 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
73 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
74 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
75 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
76 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
77 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
78 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
79 ; WIN64: vmovaps {{%ymm([6-9]|1[0-5])}}, {{.*(%rbp).*}} # 32-byte Spill
[all …]
Dsse-intel-ocl.ll73 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
74 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
75 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
76 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
77 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
78 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
79 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
80 ; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
Davx512-mask-spills.ll12 ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Folded Spill
14 ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Folded Spill
37 ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Folded Spill
39 ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Folded Spill
62 ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Folded Spill
64 ; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%rsp) ## 2-byte Folded Spill
86 ; CHECK-NEXT: kmovd %k0, {{[0-9]+}}(%rsp) ## 4-byte Folded Spill
88 ; CHECK-NEXT: kmovd %k0, (%rsp) ## 4-byte Folded Spill
110 ; CHECK-NEXT: kmovq %k0, {{[0-9]+}}(%rsp) ## 8-byte Folded Spill
112 ; CHECK-NEXT: kmovq %k0, {{[0-9]+}}(%rsp) ## 8-byte Folded Spill
Davx512-intel-ocl.ll65 ; WIN64: vmovups %zmm21, {{.*(%rbp).*}} # 64-byte Spill
66 ; WIN64: vmovups %zmm6, {{.*(%rbp).*}} # 64-byte Spill
72 ; X64: kmovq %k7, {{.*}}(%rsp) ## 8-byte Folded Spill
73 ; X64: kmovq %k6, {{.*}}(%rsp) ## 8-byte Folded Spill
74 ; X64: kmovq %k5, {{.*}}(%rsp) ## 8-byte Folded Spill
75 ; X64: kmovq %k4, {{.*}}(%rsp) ## 8-byte Folded Spill
76 ; X64: vmovups %zmm31, {{.*}}(%rsp) ## 64-byte Spill
77 ; X64: vmovups %zmm16, {{.*}}(%rsp) ## 64-byte Spill
Dstatepoint-stackmap-format.ll127 ; Indirect Spill Slot [RSP+0]
147 ; Indirect Spill Slot [RSP+16]
152 ; Indirect Spill Slot [RSP+8]
157 ; Indirect Spill Slot [RSP+16]
162 ; Indirect Spill Slot [RSP+16]
194 ; Indirect Spill Slot [RSP+0]
214 ; Indirect Spill Slot [RSP+16]
219 ; Indirect Spill Slot [RSP+8]
224 ; Indirect Spill Slot [RSP+16]
229 ; Indirect Spill Slot [RSP+16]
D2013-10-14-FastISel-incorrect-vreg.ll19 ; Spill %arg2.
21 ; Spill %loaded_ptr.
58 ; Spill %arg2.
60 ; Spill %loaded_ptr.
97 ; Spill %arg2.
99 ; Spill %loaded_ptr.
Dunaligned-spill-folding.ll37 ; UNALIGNED: movdqu {{.*}} # 16-byte Folded Spill
42 ; ALIGNED: movdqa {{.*}} # 16-byte Spill
47 ; FORCEALIGNED: movdqa {{.*}} # 16-byte Spill
Dvzero-excess.ll12 ; CHECK-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
38 ; CHECK-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
54 ; CHECK-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
80 ; CHECK-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
Dsad.ll163 ; SSE2-NEXT: movdqa %xmm5, -{{[0-9]+}}(%rsp) # 16-byte Spill
164 ; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp) # 16-byte Spill
165 ; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) # 16-byte Spill
166 ; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp) # 16-byte Spill
259 ; SSE2-NEXT: movdqa %xmm6, -{{[0-9]+}}(%rsp) # 16-byte Spill
410 ; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) # 16-byte Spill
414 ; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) # 16-byte Spill
417 ; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) # 16-byte Spill
426 ; SSE2-NEXT: movdqa %xmm12, {{[0-9]+}}(%rsp) # 16-byte Spill
427 ; SSE2-NEXT: movdqa %xmm7, -{{[0-9]+}}(%rsp) # 16-byte Spill
[all …]
Dsink-cheap-instructions.ll7 ; CHECK: Spill
8 ; SINK-NOT: Spill
Dcatchret-regmask.ll32 ; CHECK: movq %rcx, -[[arg_slot:[0-9]+]](%rbp) # 8-byte Spill
70 ; CHECK: movq %rax, -[[val_slot]](%rbp) # 8-byte Spill
Dvector-half-conversions.ll2364 ; ALL-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
2398 ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
2412 ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
2445 ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
2459 ; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
2492 ; AVX512-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
2504 ; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
2541 ; AVX1-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
2555 ; AVX1-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
2589 ; AVX2-NEXT: vmovupd %ymm0, (%rsp) # 32-byte Spill
[all …]
Dwin32-seh-catchpad-realign.ll50 ; Spill EBP
52 ; Spill ESP
Dwin-catchpad-varargs.ll38 ; X64: movl $-1, -20(%rbp) # 4-byte Folded Spill
60 ; X64: movl %eax, -20(%rbp) # 4-byte Spill
Dmasked_memop.ll3719 ; AVX1-NEXT: movl %r9d, {{[0-9]+}}(%rsp) ## 4-byte Spill
3720 ; AVX1-NEXT: movl %r8d, (%rsp) ## 4-byte Spill
3721 ; AVX1-NEXT: movl %ecx, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3722 ; AVX1-NEXT: movl %edx, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3723 ; AVX1-NEXT: movl %esi, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3731 ; AVX1-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3733 ; AVX1-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3735 ; AVX1-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3737 ; AVX1-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
3739 ; AVX1-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
[all …]
Dstatepoint-allocas.ll91 ; Direct Spill Slot [RSP+0]
120 ; Direct Spill Slot [RSP+0]
/external/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.cpp202 struct SpilledReg Spill; in getSpilledReg() local
203 Spill.Lane = Lane; in getSpilledReg()
210 return Spill; in getSpilledReg()
222 Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; in getSpilledReg()
223 return Spill; in getSpilledReg()
DSIMachineFunctionInfo.h291 void setHasSpilledSGPRs(bool Spill = true) {
292 HasSpilledSGPRs = Spill;
299 void setHasSpilledVGPRs(bool Spill = true) {
300 HasSpilledVGPRs = Spill;
DSIRegisterInfo.cpp528 struct SIMachineFunctionInfo::SpilledReg Spill = in eliminateFrameIndex() local
531 if (Spill.hasReg()) { in eliminateFrameIndex()
534 Spill.VGPR) in eliminateFrameIndex()
536 .addImm(Spill.Lane); in eliminateFrameIndex()
592 struct SIMachineFunctionInfo::SpilledReg Spill = in eliminateFrameIndex() local
595 if (Spill.hasReg()) { in eliminateFrameIndex()
599 .addReg(Spill.VGPR) in eliminateFrameIndex()
600 .addImm(Spill.Lane) in eliminateFrameIndex()
/external/llvm/lib/CodeGen/
DRegAllocBasic.cpp191 LiveInterval &Spill = *Intfs[i]; in spillInterferences() local
194 if (!VRM->hasPhys(Spill.reg)) in spillInterferences()
199 Matrix->unassign(Spill); in spillInterferences()
202 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, nullptr, &DeadRemats); in spillInterferences()
DInlineSpiller.cpp123 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
125 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
1054 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, in addToMergeableSpills() argument
1057 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
1060 MergeableSpills[MIdx].insert(&Spill); in addToMergeableSpills()
1066 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill, in rmFromMergeableSpills() argument
1071 SlotIndex Idx = LIS.getInstructionIndex(Spill); in rmFromMergeableSpills()
1074 return MergeableSpills[MIdx].erase(&Spill); in rmFromMergeableSpills()
1164 for (const auto Spill : Spills) { in getVisitOrders() local
1165 MachineBasicBlock *Block = Spill->getParent(); in getVisitOrders()
/external/llvm/test/MC/Mips/
Delf-tls.s34 sw $ra, 20($sp) # 4-byte Folded Spill
66 sw $ra, 20($sp) # 4-byte Folded Spill
98 sw $ra, 20($sp) # 4-byte Folded Spill
Delf-N64.s34 sd $ra, 8($sp) # 8-byte Folded Spill
35 sd $gp, 0($sp) # 8-byte Folded Spill
Dr-mips-got-disp.s27 sd $ra, 8($sp) # 8-byte Folded Spill
28 sd $gp, 0($sp) # 8-byte Folded Spill
/external/llvm/test/CodeGen/Mips/
Dstldst.ll36 ; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill
38 ; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill

123