Searched refs:Src0IsKill (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4485 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem() local
4501 Src0IsKill); in selectRem()
4549 bool Src0IsKill = hasTrivialKill(Src0); in selectMul() local
4552 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4563 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul() local
4570 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul()
4764 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv() local
4767 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); in selectSDiv()
4794 Src0IsKill, AArch64CC::LT); in selectSDiv()
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| D | AArch64InstrInfo.cpp | 3291 bool Src0IsKill = MUL->getOperand(1).isKill(); in genFusedMultiply() local
3309 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
3315 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
3321 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
3355 bool Src0IsKill = MUL->getOperand(1).isKill(); in genMaddR() local
3370 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()
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