Searched refs:Src0Reg (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4482 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectRem() local
4483 if (!Src0Reg) in selectRem()
4494 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false, in selectRem()
4500 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4546 unsigned Src0Reg = getRegForValue(Src0); in selectMul() local
4547 if (!Src0Reg) in selectMul()
4552 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4560 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectMul() local
4561 if (!Src0Reg) in selectMul()
4570 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); in selectMul()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 269 unsigned Src0Reg,
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| D | R600InstrInfo.cpp | 1264 unsigned Src0Reg, in buildDefaultInstruction() argument
1277 .addReg(Src0Reg) // $src0 in buildDefaultInstruction()
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| D | SIInstrInfo.cpp | 2108 unsigned Src0Reg = Src0.getReg(); in legalizeOperandsVOP2() local
2120 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill); in legalizeOperandsVOP2()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1684 unsigned Src0Reg = getRegForValue(I->getOperand(0)); in selectDivRem() local
1686 if (!Src0Reg || !Src1Reg) in selectDivRem()
1689 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
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