Searched refs:Src0VT (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 1400 class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
1406 !if(!eq(Src0VT.Size, 64),
1408 !if(!eq(Src0VT.Size, 64),
1422 field ValueType Src0VT = ArgVT[1];
1428 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1430 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1433 field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
1435 field RegisterClass Src0SDWA = getVregSrcForVT<Src0VT>.ret;
1440 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1441 field bit HasModifiers = hasModifiers<Src0VT>.ret;
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1534 EVT Src0VT = Src0.getValueType(); in SplitVecOp_VSELECT() local
1544 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT); in SplitVecOp_VSELECT()
1557 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
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