Searched refs:Src1IsKill (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2561 bool Src1IsKill = hasTrivialKill(Src1Val); in optimizeSelect() local
2569 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2570 Src1IsKill = true; in optimizeSelect()
2573 Src1IsKill, Src2Reg, Src2IsKill); in optimizeSelect()
2689 bool Src1IsKill = hasTrivialKill(SI->getTrueValue()); in selectSelect() local
2698 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
4490 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectRem() local
4500 Src1Reg, Src1IsKill, Src0Reg, in selectRem()
4568 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectMul() local
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| D | AArch64InstrInfo.cpp | 3293 bool Src1IsKill = MUL->getOperand(2).isKill(); in genFusedMultiply() local
3310 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3316 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
3322 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
3357 bool Src1IsKill = MUL->getOperand(2).isKill(); in genMaddR() local
3371 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
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