Searched refs:SrcLane (Results 1 – 3 of 3) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 4374 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; in setExecutionDomain() local
4376 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); in setExecutionDomain()
4379 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) in setExecutionDomain()
4391 .addImm(SrcLane); in setExecutionDomain()
4422 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4426 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4433 if (SrcLane == DstLane) in setExecutionDomain()
4441 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4445 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4452 if (SrcLane != DstLane) in setExecutionDomain()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5687 int SrcLane = ShuffleMask[Anomaly]; in LowerVECTOR_SHUFFLE() local
5688 if (SrcLane >= NumInputElements) { in LowerVECTOR_SHUFFLE()
5690 SrcLane -= VT.getVectorNumElements(); in LowerVECTOR_SHUFFLE()
5692 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64); in LowerVECTOR_SHUFFLE()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 11081 int SrcLane = (M % NumElts) / NumLaneElts; in lowerShuffleAsRepeatedMaskAndLanePermute() local
11082 int SrcSubLane = (SrcLane * SubLaneScale) + in lowerShuffleAsRepeatedMaskAndLanePermute()
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