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Searched refs:SrcR (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DRDFCopy.cpp36 RegisterRef SrcR = { Src.getReg(), Src.getSubReg() }; in interpretAsCopy() local
38 if (!TargetRegisterInfo::isVirtualRegister(SrcR.Reg)) in interpretAsCopy()
41 if (MRI.getRegClass(DstR.Reg) != MRI.getRegClass(SrcR.Reg)) in interpretAsCopy()
44 if (!TargetRegisterInfo::isPhysicalRegister(SrcR.Reg)) in interpretAsCopy()
48 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonGenInsert.cpp432 : SrcR(SR), InsR(IR), Wdh(W), Off(O) {} in IFRecord()
433 unsigned SrcR, InsR; member
447 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
448 OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) in operator <<()
488 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
637 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
640 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm()
839 unsigned SrcR = *I; in findRecordInsertForms() local
841 const BitTracker::RegisterCell &AC = CMS->lookup(SrcR); in findRecordInsertForms()
874 if (!isValidInsertForm(VR, SrcR, InsR, L, S)) in findRecordInsertForms()
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DHexagonRDFOpt.cpp98 auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in interpretAsCopy() argument
99 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonFrameLowering.cpp1381 unsigned SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1383 !Hexagon::ModRegsRegClass.contains(SrcR)) in expandCopy()
1403 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1415 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1466 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1488 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1549 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1550 unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg); in expandStoreVec2()
1551 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg); in expandStoreVec2()
1653 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
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/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.cpp1852 Variable *SrcR; in legalizeMovFp() local
1854 SrcR = Target->makeReg( in legalizeMovFp()
1857 SrcR = Target->makeReg( in legalizeMovFp()
1860 Sandboxer(Target).sw(SrcR, Addr); in legalizeMovFp()
1883 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1884 if (Dest->hasReg() && SrcR->hasReg()) { in legalizeMov()
1889 const bool IsSrcGPR = RegMIPS32::isGPRReg(SrcR->getRegNum()); in legalizeMov()
1890 const RegNumT SRegNum = SrcR->getRegNum(); in legalizeMov()
1973 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1974 assert(SrcR->hasReg()); in legalizeMov()
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DIceTargetLoweringARM32.cpp1876 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1877 assert(SrcR->hasReg()); in legalizeMov()
1878 assert(!SrcR->isRematerializable()); in legalizeMov()
1882 .str(SrcR, createMemOperand(DestTy, StackOrFrameReg, Offset), in legalizeMov()
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp388 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
391 .addOperand(SrcR) in processInstructionForSLM()