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Searched refs:SrcReg2 (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp180 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
188 SrcReg2 = 0; in analyzeCompare()
194 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
208 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
213 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
214 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
306 if (SrcReg2 != 0) in optimizeCompareInstr()
332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
384 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
DLanaiInstrInfo.h95 unsigned &SrcReg2, int &CmpMask,
102 unsigned SrcReg2, int CmpMask, int CmpValue,
/external/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp407 unsigned SrcReg2 = in fuseCompareOperations() local
412 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareOperations()
459 if (SrcReg2) in fuseCompareOperations()
460 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareOperations()
DSystemZInstrInfo.h172 unsigned &SrcReg2, int &Mask, int &Value) const override;
174 unsigned SrcReg2, int Mask, int Value,
DSystemZInstrInfo.cpp433 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
440 SrcReg2 = 0; in analyzeCompare()
515 MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask, in optimizeCompareInstr() argument
517 assert(!SrcReg2 && "Only optimizing constant comparisons so far"); in optimizeCompareInstr()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h250 unsigned &SrcReg2, int &Mask, int &Value) const override;
253 unsigned SrcReg2, int Mask, int Value,
DPPCFastISel.cpp876 unsigned SrcReg2 = 0; in PPCEmitCmp() local
878 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
879 if (SrcReg2 == 0) in PPCEmitCmp()
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
893 SrcReg2 = ExtReg; in PPCEmitCmp()
899 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1262 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1263 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1267 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1270 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
DPPCInstrInfo.cpp1500 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
1511 SrcReg2 = 0; in analyzeCompare()
1522 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1528 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
1635 if (SrcReg2 != 0) in optimizeCompareInstr()
1672 Instr.getOperand(2).getReg() == SrcReg2) || in optimizeCompareInstr()
1673 (Instr.getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
1719 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h166 unsigned &SrcReg2, int &CmpMask,
171 unsigned SrcReg2, int CmpMask, int CmpValue,
DAArch64InstrInfo.cpp693 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
712 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
721 SrcReg2 = 0; in analyzeCompare()
731 SrcReg2 = 0; in analyzeCompare()
883 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
913 if (CmpValue != 0 || SrcReg2 != 0) in optimizeCompareInstr()
3294 unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); in genFusedMultiply() local
3303 if (TargetRegisterInfo::isVirtualRegister(SrcReg2)) in genFusedMultiply()
3304 MRI.constrainRegClass(SrcReg2, RC); in genFusedMultiply()
3311 .addReg(SrcReg2, getKillRegState(Src2IsKill)); in genFusedMultiply()
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/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1425 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1427 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1428 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1436 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1437 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1444 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1446 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
DARMBaseInstrInfo.h254 unsigned &SrcReg2, int &CmpMask,
262 unsigned SrcReg2, int CmpMask, int CmpValue,
DARMBaseInstrInfo.cpp2288 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
2295 SrcReg2 = 0; in analyzeCompare()
2302 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
2309 SrcReg2 = 0; in analyzeCompare()
2362 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr() argument
2369 OI->getOperand(2).getReg() == SrcReg2) || in isRedundantFlagInstr()
2370 (OI->getOperand(1).getReg() == SrcReg2 && in isRedundantFlagInstr()
2392 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr() argument
2430 if (SrcReg2 != 0) in optimizeCompareInstr()
2459 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) { in optimizeCompareInstr()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrInfo.h504 unsigned &SrcReg2, int &CmpMask,
511 unsigned SrcReg2, int CmpMask, int CmpValue,
DX86InstrInfo.cpp2928 unsigned SrcReg2; in convertToThreeAddress() local
2931 SrcReg2, isKill2, isUndef2, ImplicitOp2)) in convertToThreeAddress()
2941 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
2948 LV->replaceKillInstruction(SrcReg2, MI, *NewMI); in convertToThreeAddress()
4828 unsigned &SrcReg2, int &CmpMask, in analyzeCompare() argument
4840 SrcReg2 = 0; in analyzeCompare()
4850 SrcReg2 = 0; in analyzeCompare()
4859 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
4871 SrcReg2 = 0; in analyzeCompare()
4880 SrcReg2 = MI.getOperand(1).getReg(); in analyzeCompare()
[all …]
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp565 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
567 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
569 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) in optimizeCmpInstr()
573 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1166 unsigned &SrcReg2, int &Mask, int &Value) const { in analyzeCompare() argument
1174 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr() argument
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h251 unsigned &SrcReg2, int &Mask, int &Value) const override;
DHexagonInstrInfo.cpp1524 unsigned &SrcReg2, int &Mask, in analyzeCompare() argument
1585 SrcReg2 = MI.getOperand(2).getReg(); in analyzeCompare()
1600 SrcReg2 = 0; in analyzeCompare()
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_program_alu.c83 struct rc_src_register SrcReg2) in emit3() argument
95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3()