Searched refs:Swz (Results 1 – 5 of 5) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_emulate_loops.c | 53 rc_swizzle Swz; member
124 (1 << GET_SWZ(count_inst->Swz,0) != mask)){ in get_incr_amount()
143 inst->U.I.SrcReg[0].Swizzle == count_inst->Swz){ in get_incr_amount()
147 inst->U.I.SrcReg[1].Swizzle == count_inst->Swz){ in get_incr_amount()
232 count_inst.Swz = counter->Swizzle; in try_unroll_loop()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 383 R600InstrInfo::BankSwizzle Swz) { in Swizzle() argument
386 switch (Swz) { in Swizzle()
411 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { in getTransSwizzle() argument
412 switch (Swz) { in getTransSwizzle()
440 const std::vector<R600InstrInfo::BankSwizzle> &Swz, in isLegalUpTo() argument
447 Swizzle(IGSrcs[i], Swz[i]); in isLegalUpTo()
453 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 && in isLegalUpTo()
454 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) { in isLegalUpTo()
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| D | R600ISelLowering.h | 62 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
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| D | R600InstrInfo.h | 120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
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| D | R600ISelLowering.cpp | 1918 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], in OptimizeSwizzle()
1927 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue(); in OptimizeSwizzle()
1929 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1935 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue(); in OptimizeSwizzle()
1937 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
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