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Searched refs:TEST5 (Results 1 – 23 of 23) sorted by relevance

/external/valgrind/none/tests/mips64/
Dbranch_and_jump_instructions.c152 #define TEST5(instruction, RDval, RSval, RD, RS) \ macro
231 TEST5("bgezal", 0, 0, 2, 3); in main()
232 TEST5("bgezal", 1, 1, 3, 4); in main()
233 TEST5("bgezal", 2, 0xffffffff, 4, 5); in main()
234 TEST5("bgezal", 3, 0xffffffff, 5, 6); in main()
235 TEST5("bgezal", 4, 0xfffffffe, 6, 7); in main()
236 TEST5("bgezal", 5, 0xffffffff, 7, 8); in main()
237 TEST5("bgezal", 6, 0x5, 8, 9); in main()
238 TEST5("bgezal", 7, -3, 9, 10); in main()
239 TEST5("bgezal", 8, 125, 10, 11); in main()
[all …]
Dmove_instructions.c178 #define TEST5(instruction, RDval, RSval, RD, RS) \ macro
358 TEST5("movf", 0xaaaaaaaa, 0x80000000, t0, t1); in main()
359 TEST5("movf", 0xccccffff, 0xffffffff, t1, t2); in main()
360 TEST5("movf", 0xffffaaaa, 0xaaaaffff, t3, t1); in main()
361 TEST5("movf", 0x0, 0xffffffff, t3, t0); in main()
367 TEST5("movt", 0x0, 0xffffffff, t0, t1); in main()
368 TEST5("movt", 0x11111111, 0xeeeeffff, t1, t2); in main()
369 TEST5("movt", 0x5555ffff, 0xffffffff, t3, t1); in main()
370 TEST5("movt", 0xeeeeeeee, 0xffffeeee, t3, t0); in main()
Dfpu_load_store.c23 TEST5("ldxc1", i, reg_val1); in main()
26 TEST5("ldxc1", i, reg_val2); in main()
Darithmetic_instruction.c210 TEST5("madd $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
217 TEST5("maddu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
224 TEST5("msub $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
233 TEST5("msubu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); in main()
Dmacro_load_store.h104 #define TEST5(instruction, offset, mem) \ macro
Dmacro_int.h71 #define TEST5(instruction, RSval, RTval, RS, RT) \ macro
/external/clang/test/CodeGenObjC/
Darc-unopt.m59 // CHECK: [[X:%.*]] = alloca [[TEST5:%.*]]*,
60 // CHECK-NEXT: [[Y:%.*]] = alloca [[TEST5:%.*]]*,
61 // CHECK-NEXT: store [[TEST5]]* null, [[TEST5]]** [[X]],
62 // CHECK-NEXT: store [[TEST5]]* null, [[TEST5]]** [[Y]],
63 // CHECK-NEXT: [[T0:%.*]] = load [[TEST5]]*, [[TEST5]]** [[Y]],
64 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST5]]** [[X]] to i8**
65 // CHECK-NEXT: [[T2:%.*]] = bitcast [[TEST5]]* [[T0]] to i8*
67 // CHECK-NEXT: [[T3:%.*]] = icmp ne [[TEST5]]* [[T0]], null
Darc.m212 // CHECK: [[X:%.*]] = alloca [[TEST5:%.*]]*,
214 // CHECK-NEXT: bitcast [[TEST5]]* {{%.*}} to i8*
216 // CHECK-NEXT: [[PARMX:%.*]] = bitcast i8* {{%.*}} to [[TEST5]]*
217 // CHECK-NEXT: store [[TEST5]]* [[PARMX]], [[TEST5]]** [[X]]
221 // CHECK-NEXT: load [[TEST5]]*, [[TEST5]]** [[X]]
232 // CHECK-NEXT: load [[TEST5]]*, [[TEST5]]** [[X]]
246 // CHECK-NEXT: [[T0:%.*]] = load [[TEST5]]*, [[TEST5]]** [[X]]
247 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST5]]* [[T0]] to i8*
/external/swiftshader/third_party/LLVM/test/MC/AsmParser/
Ddirective_ascii.s30 # CHECK: TEST5:
32 TEST5: label
Ddirective_values.s39 TEST5: label
41 # CHECK: TEST5:
/external/llvm/test/MC/AsmParser/
Ddirective_ascii.s30 # CHECK: TEST5:
32 TEST5: label
Ddirective_values.s39 TEST5: label
41 # CHECK: TEST5:
Ddirective_fill.s31 # CHECK: TEST5
33 TEST5: label
/external/llvm/test/MC/ARM/
Deh-directive-multiple-offsets.s131 @ TEST5: Check .setfp, .save, .setfp directive.
133 .section .TEST5
164 @ CHECK: Name: .ARM.extab.TEST5
Deh-directive-pad.s174 @ TEST5
176 .section .TEST5
221 @ CHECK: Name: .ARM.extab.TEST5
Deh-directive-setfp.s186 @ TEST5
188 .section .TEST5
234 @ CHECK: Name: .ARM.extab.TEST5
Deh-directive-save.s303 @ TEST5
305 .section .TEST5
338 @ CHECK: Name: .ARM.extab.TEST5
Deh-directive-setfp-diagnostics.s76 @ TEST5: .setfp with non-sp register as second operand
/external/clang/test/Frontend/
Dverify.c101 #ifdef TEST5
/external/clang/test/Sema/
Dwarn-extern-main.c28 #elif TEST5
/external/clang/test/CXX/basic/basic.start/basic.start.main/
Dp3.cpp33 #elif TEST5
Dp2.cpp52 #elif TEST5
/external/bison/data/m4sugar/
Dm4sugar.m41782 # | m4_defun([TEST5], [5 TEST4 m4_require([TEST4])])
1783 # | TEST5 => 5 4