TMP1 (reference) in projects: external - OpenGrok search results

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Searched refs:TMP1 (Results 1 – 25 of 66) sorted by relevance

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/external/pcre/dist2/src/
D	pcre2_jit_compile.c	505 #define TMP1 SLJIT_R0 macro 1686 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame() 1689 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame() 1702 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame() 1705 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame() 1715 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame() 1718 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame() 1724 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame() 1727 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame() 1733 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->capture_last_ptr); in init_frame() [all …]
/external/boringssl/src/crypto/cipher_extra/asm/
D	aes128gcmsiv-x86_64.pl	`85 my $TMP1 = "%xmm2"; 95 vpclmulqdq \$0x00, $TMP0, $T, $TMP1 102 vpxor $TMP3, $TMP1, $TMP1 105 vpclmulqdq \$0x10, poly(%rip), $TMP1, $TMP2 106 vpshufd \$78, $TMP1, $TMP3 107 vpxor $TMP3, $TMP2, $TMP1 109 vpclmulqdq \$0x10, poly(%rip), $TMP1, $TMP2 110 vpshufd \$78, $TMP1, $TMP3 111 vpxor $TMP3, $TMP2, $TMP1 113 vpxor $TMP4, $TMP1, $T [all …]`
/external/llvm/test/Transforms/InstCombine/
D	or-fcmp.ll	`27 ; CHECK-NEXT: [[TMP1:%.]] = fcmp oeq double %a, %b 28 ; CHECK-NEXT: ret i1 [[TMP1]] 49 ; CHECK-NEXT: [[TMP1:%.]] = fcmp oge double %a, %b 50 ; CHECK-NEXT: ret i1 [[TMP1]] 60 ; CHECK-NEXT: [[TMP1:%.]] = fcmp ogt double %a, %b 61 ; CHECK-NEXT: ret i1 [[TMP1]] 82 ; CHECK-NEXT: [[TMP1:%.]] = fcmp oge double %a, %b 83 ; CHECK-NEXT: ret i1 [[TMP1]] 93 ; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double %a, %b 94 ; CHECK-NEXT: ret i1 [[TMP1]] [all …]`
D	and-fcmp.ll	`53 ; CHECK-NEXT: [[TMP1:%.]] = fcmp oeq double %a, %b 54 ; CHECK-NEXT: ret i1 [[TMP1]] 84 ; CHECK-NEXT: [[TMP1:%.]] = fcmp ogt double %a, %b 85 ; CHECK-NEXT: ret i1 [[TMP1]] 105 ; CHECK-NEXT: [[TMP1:%.]] = fcmp oeq double %a, %b 106 ; CHECK-NEXT: ret i1 [[TMP1]] 116 ; CHECK-NEXT: [[TMP1:%.]] = fcmp ogt double %a, %b 117 ; CHECK-NEXT: ret i1 [[TMP1]] 127 ; CHECK-NEXT: [[TMP1:%.*]] = fcmp oge double %a, %b 128 ; CHECK-NEXT: ret i1 [[TMP1]] [all …]`
D	x86-avx.ll	44 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinit… 45 ; CHECK-NEXT: ret <4 x float> [[TMP1]] 53 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <8 x float> %v, <8 x float> undef, <8 x i32> <i32 0, … 54 ; CHECK-NEXT: ret <8 x float> [[TMP1]] 62 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <2 x double> %v, <2 x double> undef, <2 x i32> zeroin… 63 ; CHECK-NEXT: ret <2 x double> [[TMP1]] 71 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <4 x double> %v, <4 x double> undef, <4 x i32> <i32 0… 72 ; CHECK-NEXT: ret <4 x double> [[TMP1]] 82 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> <i32 3, … 83 ; CHECK-NEXT: ret <4 x float> [[TMP1]] [all …]
D	and-or.ll	`6 ; CHECK-NEXT: [[TMP1:%.]] = and i32 %a, 1 7 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 19 ; CHECK-NEXT: [[TMP1:%.]] = and i32 %a, 1 20 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 32 ; CHECK-NEXT: [[TMP1:%.]] = and i32 %a, 1 33 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b 45 ; CHECK-NEXT: [[TMP1:%.]] = and i32 %a, 1 46 ; CHECK-NEXT: [[TMP3:%.]] = or i32 [[TMP1]], %b`
D	x86-vector-shifts.ll	19 ; CHECK-NEXT: [[TMP1:%.]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,… 20 ; CHECK-NEXT: ret <8 x i16> [[TMP1]] 28 ; CHECK-NEXT: [[TMP1:%.]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,… 29 ; CHECK-NEXT: ret <8 x i16> [[TMP1]] 45 ; CHECK-NEXT: [[TMP1:%.]] = ashr <4 x i32> %v, <i32 15, i32 15, i32 15, i32 15> 46 ; CHECK-NEXT: ret <4 x i32> [[TMP1]] 54 ; CHECK-NEXT: [[TMP1:%.]] = ashr <4 x i32> %v, <i32 31, i32 31, i32 31, i32 31> 55 ; CHECK-NEXT: ret <4 x i32> [[TMP1]] 71 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15… 72 ; CHECK-NEXT: ret <16 x i16> [[TMP1]] [all …]
D	x86-sse2.ll	7 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <2 x double> undef, double %a, i32 0 8 ; CHECK-NEXT: [[TMP2:%.]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP1]]) 32 ; CHECK-NEXT: [[TMP1:%.]] = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x … 33 ; CHECK-NEXT: ret <2 x double> [[TMP1]] 42 ; CHECK-NEXT: [[TMP1:%.]] = fadd double %a, %b 43 ; CHECK-NEXT: ret double [[TMP1]] 69 ; CHECK-NEXT: [[TMP1:%.]] = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %a, <2 x … 70 ; CHECK-NEXT: ret <2 x double> [[TMP1]] 79 ; CHECK-NEXT: [[TMP1:%.]] = fsub double %a, %b 80 ; CHECK-NEXT: ret double [[TMP1]] [all …]
D	exact.ll	`140 ; CHECK-NEXT: [[TMP1:%.]] = icmp ne i64 %X, 0 141 ; CHECK-NEXT: ret i1 [[TMP1]] 150 ; CHECK-NEXT: [[TMP1:%.]] = icmp eq i64 %X, 0 151 ; CHECK-NEXT: ret i1 [[TMP1]] 160 ; CHECK-NEXT: [[TMP1:%.]] = icmp eq i64 %X, 0 161 ; CHECK-NEXT: ret i1 [[TMP1]] 170 ; CHECK-NEXT: [[TMP1:%.]] = icmp eq i64 %X, 5 171 ; CHECK-NEXT: ret i1 [[TMP1]] 180 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5 181 ; CHECK-NEXT: ret i1 [[TMP1]] [all …]`
D	x86-avx2.ll	28 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> zeroinitial… 29 ; CHECK-NEXT: ret <8 x i32> [[TMP1]] 37 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> zeroini… 38 ; CHECK-NEXT: ret <8 x float> [[TMP1]] 48 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 7, i32… 49 ; CHECK-NEXT: ret <8 x i32> [[TMP1]] 57 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <8 x float> %a0, <8 x float> undef, <8 x i32> <i32 7,… 58 ; CHECK-NEXT: ret <8 x float> [[TMP1]] 68 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 undef,… 69 ; CHECK-NEXT: ret <8 x i32> [[TMP1]] [all …]
D	load-cmp.ll	47 ; CHECK-NEXT: [[TMP1:%.]] = trunc i64 %X to i32 48 ; CHECK-NEXT: [[R:%.]] = icmp eq i32 [[TMP1]], 9 59 ; CHECK-NEXT: [[TMP1:%.]] = trunc i32 %x to i16 60 ; CHECK-NEXT: [[R:%.]] = icmp eq i16 [[TMP1]], 9 95 ; CHECK-NEXT: [[TMP1:%.]] = lshr i32 933, %X 96 ; CHECK-NEXT: [[TMP2:%.]] = and i32 [[TMP1]], 1 108 ; CHECK-NEXT: [[TMP1:%.]] = sext i16 %X to i32 109 ; CHECK-NEXT: [[TMP2:%.]] = lshr i32 933, [[TMP1]] 122 ; CHECK-NEXT: [[TMP1:%.]] = icmp eq i32 %X, 2 124 ; CHECK-NEXT: [[R:%.]] = or i1 [[TMP1]], [[TMP2]] [all …]
D	x86-sse.ll	7 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <4 x float> undef, float %a, i32 0 8 ; CHECK-NEXT: [[TMP2:%.]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]]) 36 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <4 x float> undef, float %a, i32 0 37 ; CHECK-NEXT: [[TMP2:%.]] = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> [[TMP1]]) 65 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <4 x float> undef, float %a, i32 0 66 ; CHECK-NEXT: [[TMP2:%.]] = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[TMP1]]) 94 ; CHECK-NEXT: [[TMP1:%.]] = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a, <4 x flo… 95 ; CHECK-NEXT: ret <4 x float> [[TMP1]] 106 ; CHECK-NEXT: [[TMP1:%.]] = fadd float %a, %b 107 ; CHECK-NEXT: ret float [[TMP1]] [all …]
D	x86-sse4a.ll	10 ; CHECK-NEXT: [[TMP1:%.]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %… 11 ; CHECK-NEXT: ret <2 x i64> [[TMP1]] 35 ; CHECK-NEXT: [[TMP1:%.]] = call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 15) 36 ; CHECK-NEXT: ret <2 x i64> [[TMP1]] 64 ; CHECK-NEXT: [[TMP1:%.]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 2… 65 ; CHECK-NEXT: ret <2 x i64> [[TMP1]] 73 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> %x to <16 x i8> 74 ; CHECK-NEXT: [[TMP2:%.]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 undef, i8 undef, i8… 84 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> %x to <16 x i8> 85 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 undef, i8 0, i8 0, … [all …]
D	or.ll	`138 ; CHECK-NEXT: [[TMP1:%.]] = icmp ne i32 %A, %B 139 ; CHECK-NEXT: ret i1 [[TMP1]] 150 ; CHECK-NEXT: [[TMP1:%.]] = icmp ule i32 %A, %B 151 ; CHECK-NEXT: ret i1 [[TMP1]] 187 ; CHECK-NEXT: [[TMP1:%.]] = icmp ugt i32 [[A_OFF]], 49 188 ; CHECK-NEXT: ret i1 [[TMP1]] 199 ; CHECK-NEXT: [[TMP1:%.]] = or i32 %A, 1 200 ; CHECK-NEXT: [[TMP2:%.]] = icmp eq i32 [[TMP1]], 51 258 ; CHECK-NEXT: [[TMP1:%.]] = fcmp uno double %Y, %X 259 ; CHECK-NEXT: ret i1 [[TMP1]] [all …]`
D	div-shift.ll	`22 ; CHECK-NEXT: [[TMP1:%.]] = zext i32 %y to i64 23 ; CHECK-NEXT: [[TMP2:%.]] = lshr i64 %x, [[TMP1]] 35 ; CHECK-NEXT: [[TMP1:%.]] = add i32 %y, 2 36 ; CHECK-NEXT: [[TMP2:%.]] = zext i32 [[TMP1]] to i64 48 ; CHECK-NEXT: [[TMP1:%.]] = icmp ult i32 %y, 5 49 ; CHECK-NEXT: [[DOTV:%.]] = select i1 [[TMP1]], i32 5, i32 %y 63 ; CHECK-NEXT: [[TMP1:%.]] = lshr i32 %V, [[DOTV]] 64 ; CHECK-NEXT: [[TMP2:%.]] = select i1 %y, i32 [[TMP1]], i32 0`
D	x86-xop.ll	6 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <2 x double> undef, double %a, i32 0 7 ; CHECK-NEXT: [[TMP2:%.]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]]) 31 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <4 x float> undef, float %a, i32 0 32 ; CHECK-NEXT: [[TMP2:%.]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]]) 60 ; CHECK-NEXT: [[TMP1:%.]] = icmp slt <2 x i64> %a, %b 61 ; CHECK-NEXT: [[TMP2:%.]] = sext <2 x i1> [[TMP1]] to <2 x i64> 70 ; CHECK-NEXT: [[TMP1:%.]] = icmp ult <2 x i64> %a, %b 71 ; CHECK-NEXT: [[TMP2:%.]] = sext <2 x i1> [[TMP1]] to <2 x i64> 80 ; CHECK-NEXT: [[TMP1:%.]] = icmp sle <2 x i64> %a, %b 81 ; CHECK-NEXT: [[TMP2:%.]] = sext <2 x i1> [[TMP1]] to <2 x i64> [all …]
D	x86-pshufb.ll	45 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <16 x i8> %InVec, <16 x i8> undef, <16 x i32> zeroini… 46 ; CHECK-NEXT: ret <16 x i8> [[TMP1]] 59 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <32 x i8> %InVec, <32 x i8> undef, <32 x i32> <i32 0,… 60 ; CHECK-NEXT: ret <32 x i8> [[TMP1]] 71 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef… 72 ; CHECK-NEXT: ret <16 x i8> [[TMP1]] 80 ; CHECK-NEXT: [[TMP1:%.]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef… 81 ; CHECK-NEXT: ret <16 x i8> [[TMP1]] 89 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %InVec, <16 x i8> <i8 0, i8 undef, i8 undef… 90 ; CHECK-NEXT: ret <16 x i8> [[TMP1]] [all …]
D	x86-movmsk.ll	12 ; CHECK-NEXT: [[TMP1:%.]] = call i32 @llvm.x86.mmx.pmovmskb(x86_mmx %a0) 13 ; CHECK-NEXT: ret i32 [[TMP1]] 22 ; CHECK-NEXT: [[TMP1:%.]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) 23 ; CHECK-NEXT: ret i32 [[TMP1]] 32 ; CHECK-NEXT: [[TMP1:%.]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) 33 ; CHECK-NEXT: ret i32 [[TMP1]] 42 ; CHECK-NEXT: [[TMP1:%.]] = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) 43 ; CHECK-NEXT: ret i32 [[TMP1]] 52 ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) 53 ; CHECK-NEXT: ret i32 [[TMP1]] [all …]
D	and2.ll	`7 ; CHECK-NEXT: [[TMP1:%.]] = fcmp ord double %Y, %X 8 ; CHECK-NEXT: ret i1 [[TMP1]] 39 ; CHECK-NEXT: [[TMP1:%.]] = xor <4 x i32> %A, <i32 1, i32 2, i32 3, i32 4> 40 ; CHECK-NEXT: [[TMP2:%.]] = and <4 x i32> [[TMP1]], <i32 1, i32 2, i32 3, i32 4> 65 ; CHECK-NEXT: [[TMP1:%.]] = icmp eq i32 %i, 0 66 ; CHECK-NEXT: [[TMP2:%.]] = and i1 [[TMP1]], %b 79 ; CHECK-NEXT: [[TMP1:%.]] = icmp ult i32 [[I_OFF]], 13 80 ; CHECK-NEXT: ret i1 [[TMP1]]`
D	logical-select.ll	93 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> [[SIA]] to <4 x i32> 95 ; CHECK-NEXT: [[TMP3:%.]] = select <4 x i1> %cmp, <4 x i32> [[TMP1]], <4 x i32> [[TMP2]] 115 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> [[SIA]] to <4 x i32> 117 ; CHECK-NEXT: [[TMP3:%.]] = select <4 x i1> %cmp, <4 x i32> [[TMP1]], <4 x i32> [[TMP2]] 137 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> [[SIA]] to <4 x i32> 139 ; CHECK-NEXT: [[TMP3:%.]] = select <4 x i1> %cmp, <4 x i32> [[TMP1]], <4 x i32> [[TMP2]] 159 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> [[SIA]] to <4 x i32> 161 ; CHECK-NEXT: [[TMP3:%.]] = select <4 x i1> %cmp, <4 x i32> [[TMP1]], <4 x i32> [[TMP2]] 181 ; CHECK-NEXT: [[TMP1:%.]] = bitcast <2 x i64> [[SIA]] to <4 x i32> 183 ; CHECK-NEXT: [[TMP3:%.]] = select <4 x i1> %cmp, <4 x i32> [[TMP1]], <4 x i32> [[TMP2]] [all …]
D	x86-sse41.ll	7 ; CHECK-NEXT: [[TMP1:%.]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a, <2… 8 ; CHECK-NEXT: ret <2 x double> [[TMP1]] 18 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <2 x double> undef, double %b, i32 0 19 … tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> undef, <2 x double> [[TMP1]], i32 10) 47 ; CHECK-NEXT: [[TMP1:%.]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> <float u… 48 ; CHECK-NEXT: ret <4 x float> [[TMP1]] 62 ; CHECK-NEXT: [[TMP1:%.]] = insertelement <4 x float> undef, float %b, i32 0 63 …] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> undef, <4 x float> [[TMP1]], i32 10)
D	xor.ll	`50 ; CHECK-NEXT: [[TMP1:%.]] = and i32 %A, -124 51 ; CHECK-NEXT: ret i32 [[TMP1]] 122 ; CHECK-NEXT: [[TMP1:%.]] = or i8 [[B]], 8 123 ; CHECK-NEXT: ret i8 [[TMP1]] 142 ; CHECK-NEXT: [[TMP1:%.]] = icmp ne i8 %A, %B 143 ; CHECK-NEXT: ret i1 [[TMP1]] 236 ; CHECK-NEXT: [[TMP1:%.]] = zext i1 %X to i32 237 ; CHECK-NEXT: ret i32 [[TMP1]] 249 ; CHECK-NEXT: [[TMP1:%.]] = zext i1 %X to i32 250 ; CHECK-NEXT: [[Q:%.]] = xor i32 [[TMP1]], 3 [all …]`
/external/llvm/test/CodeGen/Mips/
D	select.ll	`642 ; 32-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 643 ; 32: c.eq.d $[[TMP]], $[[TMP1]] 652 ; 32R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 653 ; 32R2: c.eq.d $[[TMP]], $[[TMP1]] 662 ; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 663 ; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]] 675 ; 64-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 676 ; 64: c.eq.d $[[TMP]], $[[TMP1]] 685 ; 64R2-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]]) 686 ; 64R2: c.eq.d $[[TMP]], $[[TMP1]] [all …]`
/external/llvm/test/Transforms/Reassociate/
D	reassoc-intermediate-fnegs.ll	`3 ; CHECK: [[TMP1:%.]] = fsub fast half 0xH8000, %a 4 ; CHECK: [[TMP2:%.]] = fadd fast half %b, [[TMP1]] 18 ; CHECK: [[TMP1:%tmp.*]] = fmul fast half %a, 0xH4500 20 ; CHECK: fadd fast half [[TMP2]], [[TMP1]]`
/external/llvm/test/CodeGen/Mips/Fast-ISel/
D	bswap1.ll	`22 ; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8 24 ; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]] 41 ; 32R1: srl $[[TMP1:[0-9]+]], $[[B_VAL]], 8 43 ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280`

12 3

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