| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 558 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
559 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
560 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, in getCastInstrCost()
561 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, in getCastInstrCost()
634 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, in getCastInstrCost()
635 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, in getCastInstrCost()
636 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, in getCastInstrCost()
637 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, in getCastInstrCost()
638 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, in getCastInstrCost()
639 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, in getCastInstrCost()
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| D | X86ISelLowering.cpp | 687 setOperationAction(ISD::TRUNCATE, VT, Expand); in X86TargetLowering()
1006 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom); in X86TargetLowering()
1007 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom); in X86TargetLowering()
1008 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom); in X86TargetLowering()
1216 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in X86TargetLowering()
1217 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom); in X86TargetLowering()
1218 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom); in X86TargetLowering()
1264 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom); in X86TargetLowering()
1265 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); in X86TargetLowering()
1266 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom); in X86TargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 109 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
110 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
125 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
126 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
253 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, in getCastInstrCost()
254 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, in getCastInstrCost()
255 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, in getCastInstrCost()
256 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 } in getCastInstrCost()
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| D | ARMSelectionDAGInfo.cpp | 92 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); in EmitSpecializedLibcall()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 667 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); in ReplaceLoadWithPromotedLoad()
806 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntBinOp()
853 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntShiftOp()
921 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); in PromoteLoad()
1083 case ISD::TRUNCATE: return visitTRUNCATE(N); in visit()
2007 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHS()
2043 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHU()
2126 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitSMUL_LOHI()
2128 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); in visitSMUL_LOHI()
2156 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitUMUL_LOHI()
[all …]
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| D | LegalizeIntegerTypes.cpp | 75 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; in PromoteIntegerResult()
524 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); in PromoteIntRes_SETCC()
597 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); in PromoteIntRes_TRUNCATE()
598 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); in PromoteIntRes_TRUNCATE()
604 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); in PromoteIntRes_TRUNCATE()
779 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; in PromoteIntegerOperand()
1043 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); in PromoteIntOp_TRUNCATE()
1112 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; in ExpandIntegerResult()
2211 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); in ExpandIntRes_TRUNCATE()
2215 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); in ExpandIntRes_TRUNCATE()
[all …]
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| D | TargetLowering.cpp | 1188 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
1190 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
1711 case ISD::TRUNCATE: { in SimplifyDemandedBits()
1754 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, in SimplifyDemandedBits()
1957 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
2008 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt); in SimplifySetCC()
2158 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in SimplifySetCC()
2198 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
2214 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
2313 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
[all …]
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| D | FastISel.cpp | 279 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, in getRegForGEPIndex()
625 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, in SelectCall()
965 return SelectCast(I, ISD::TRUNCATE); in SelectOperator()
976 return SelectCast(I, ISD::TRUNCATE); in SelectOperator()
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| D | LegalizeTypes.cpp | 987 Index = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Index); in GetVectorElementPointer()
1116 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Op); in SplitInteger()
1119 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi); in SplitInteger()
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| D | LegalizeDAG.cpp | 664 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in PerformInsertVectorEltInMemory()
1734 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); in LegalizeOp()
1773 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); in ExpandExtractFromVectorThroughStack()
1816 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); in ExpandInsertToVectorThroughStack()
2588 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); in ExpandLegalINT_TO_FP()
2593 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); in ExpandLegalINT_TO_FP()
2724 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); in PromoteLegalFP_TO_INT()
3274 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); in ExpandNode()
3277 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), in ExpandNode()
3857 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); in PromoteNode()
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| D | SelectionDAG.cpp | 887 getNode(ISD::TRUNCATE, DL, VT, Op); in getAnyExtOrTrunc()
893 getNode(ISD::TRUNCATE, DL, VT, Op); in getSExtOrTrunc()
899 getNode(ISD::TRUNCATE, DL, VT, Op); in getZExtOrTrunc()
1449 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in getShiftAmountOperand()
1932 case ISD::TRUNCATE: { in ComputeMaskedBits()
2256 case ISD::TRUNCATE: in ComputeNumSignBits()
2403 case ISD::TRUNCATE: in getNode()
2546 if (OpOpcode == ISD::TRUNCATE) { in getNode()
2552 case ISD::TRUNCATE: in getNode()
2562 if (OpOpcode == ISD::TRUNCATE) in getNode()
[all …]
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| D | LegalizeVectorTypes.cpp | 91 case ISD::TRUNCATE: in ScalarizeVectorResult()
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); in ScalarizeVecRes_INSERT_VECTOR_ELT()
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); in ScalarizeVecRes_SCALAR_TO_VECTOR()
468 case ISD::TRUNCATE: in SplitVectorResult()
990 case ISD::TRUNCATE: in SplitVectorOperand()
1289 case ISD::TRUNCATE: in WidenVectorResult()
2041 case ISD::TRUNCATE: in WidenVectorOperand()
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| D | LegalizeVectorOps.cpp | 168 case ISD::TRUNCATE: in LegalizeOp()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 940 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); in ReplaceLoadWithPromotedLoad()
1076 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntBinOp()
1123 return DAG.getNode(ISD::TRUNCATE, dl, VT, in PromoteIntShiftOp()
1192 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); in PromoteLoad()
1401 case ISD::TRUNCATE: return visitTRUNCATE(N); in visit()
2501 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHS()
2537 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); in visitMULHU()
2616 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitSMUL_LOHI()
2618 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); in visitSMUL_LOHI()
2647 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); in visitUMUL_LOHI()
[all …]
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| D | TargetLowering.cpp | 408 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
410 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
1034 case ISD::TRUNCATE: { in SimplifyDemandedBits()
1077 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, in SimplifyDemandedBits()
1401 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1470 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt); in SimplifySetCC()
1658 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); in SimplifySetCC()
1701 if (Op0.getOpcode() == ISD::TRUNCATE) in SimplifySetCC()
1718 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), in SimplifySetCC()
1837 return DAG.getNode(ISD::TRUNCATE, dl, VT, in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 88 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; in PromoteIntegerResult()
625 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); in PromoteIntRes_SETCC()
721 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); in PromoteIntRes_TRUNCATE()
722 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); in PromoteIntRes_TRUNCATE()
728 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); in PromoteIntRes_TRUNCATE()
912 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; in PromoteIntegerOperand()
1258 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op); in PromoteIntOp_TRUNCATE()
1331 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; in ExpandIntegerResult()
2511 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); in ExpandIntRes_TRUNCATE()
2516 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); in ExpandIntRes_TRUNCATE()
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 368 TRUNCATE, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 401 TRUNCATE, enumerator
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 436 if (Opcode == ISD::TRUNCATE) { in expandAddress()
614 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); in getAddressOperands()
749 case ISD::TRUNCATE: { in expandRxSBG()
934 RISBG.Input.getOpcode() != ISD::TRUNCATE) in tryRISBGZero()
1026 RxSBG[I].Input.getOpcode() != ISD::TRUNCATE) in tryRxSBG()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 320 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom); in SPUTargetLowering()
2210 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, in LowerI8Math()
2221 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, in LowerI8Math()
2233 : ISD::TRUNCATE; in LowerI8Math()
2244 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, in LowerI8Math()
2257 N1Opc = ISD::TRUNCATE; in LowerI8Math()
2262 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, in LowerI8Math()
2274 N1Opc = ISD::TRUNCATE; in LowerI8Math()
2278 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, in LowerI8Math()
2286 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, in LowerI8Math()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.cpp | 170 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); in EmitTargetCodeForMemset()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 206 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
415 Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val); in LowerCall()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1523 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0); in LowerCall()
1551 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0); in LowerCall()
1553 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1); in LowerCall()
1602 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt); in LowerCall()
1657 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0); in LowerCall()
1866 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select); in LowerSelect()
1893 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD); in LowerLOADi1()
4226 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS); in TryMULWIDECombine()
4228 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS); in TryMULWIDECombine()
4376 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 133 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
876 setTargetDAGCombine(ISD::TRUNCATE); in PPCTargetLowering()
2378 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); in LowerSETCC()
2988 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
3123 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal); in extendArgForPPC64()
3405 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
3746 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal); in LowerFormalArguments_Darwin()
4565 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
4570 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
4575 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); in LowerCallResult()
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