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Searched refs:UMIN (Results 1 – 25 of 33) sorted by relevance

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/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class1.s183UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
194UMIN v1.8h, v1.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
205UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
208UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
237UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
243UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
313UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
319UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
348UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class1_chroma.s219UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
240UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
253UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
256UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
297UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
303UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
394UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
406UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
447UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class0.s221UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
232UMIN v21.8h, v21.8h , v6.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
241UMIN v0.8h, v0.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
248UMIN v28.8h, v28.8h , v6.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
322UMIN v28.8h, v28.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class2.s342UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
351UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
439UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
444UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
450UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
463UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
520UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
526UMIN v5.8h, v5.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
656UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
662UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class3.s354UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
360UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
458UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
468UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
475UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
484UMIN v22.8h, v22.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
550UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
554UMIN v22.8h, v22.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
694UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
700UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class0_chroma.s259UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
269UMIN v19.8h, v19.8h , v6.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
292UMIN v28.8h, v28.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
304UMIN v30.8h, v30.8h , v6.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
436UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
465UMIN v24.8h, v24.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
Dihevc_sao_edge_offset_class3_chroma.s471UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
479UMIN v18.8h, v18.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
621UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
636UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
643UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
650UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
732UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
736UMIN v18.8h, v18.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
921UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
927UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class2_chroma.s488UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
493UMIN v18.8h, v18.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
621UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
643UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
656UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
664UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
742UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
746UMIN v18.8h, v18.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
909UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
914UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
/external/strace/xlat/
Datomic_ops.in9 { OR1K_ATOMIC_UMIN, "UMIN" },
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h325 SMIN, SMAX, UMIN, UMAX, enumerator
DSelectionDAG.h1170 case ISD::UMIN:
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h984 X86_INTRINSIC_DATA(avx512_mask_pminu_b_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
985 X86_INTRINSIC_DATA(avx512_mask_pminu_b_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
986 X86_INTRINSIC_DATA(avx512_mask_pminu_b_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
987 X86_INTRINSIC_DATA(avx512_mask_pminu_d_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
988 X86_INTRINSIC_DATA(avx512_mask_pminu_d_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
989 X86_INTRINSIC_DATA(avx512_mask_pminu_d_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
990 X86_INTRINSIC_DATA(avx512_mask_pminu_q_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
991 X86_INTRINSIC_DATA(avx512_mask_pminu_q_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
992 X86_INTRINSIC_DATA(avx512_mask_pminu_q_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
993 X86_INTRINSIC_DATA(avx512_mask_pminu_w_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
[all …]
DX86ISelLowering.cpp758 setOperationAction(ISD::UMIN, MVT::v16i8, Legal); in X86TargetLowering()
894 setOperationAction(ISD::UMIN, MVT::v8i16, Legal); in X86TargetLowering()
895 setOperationAction(ISD::UMIN, MVT::v4i32, Legal); in X86TargetLowering()
1053 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom); in X86TargetLowering()
1318 setOperationAction(ISD::UMIN, MVT::v16i32, Legal); in X86TargetLowering()
1319 setOperationAction(ISD::UMIN, MVT::v8i64, Legal); in X86TargetLowering()
1478 setOperationAction(ISD::UMIN, MVT::v64i8, Legal); in X86TargetLowering()
1479 setOperationAction(ISD::UMIN, MVT::v32i16, Legal); in X86TargetLowering()
1561 setOperationAction(ISD::UMIN, VT, Legal); in X86TargetLowering()
15432 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break; in LowerVSETCC()
[all …]
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h169 OP12(UMIN)
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp209 case ISD::UMIN: return "umin"; in getOperationName()
DLegalizeIntegerTypes.cpp80 case ISD::UMIN: in PromoteIntegerResult()
1381 case ISD::UMIN: in ExpandIntegerResult()
1685 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
1686 case ISD::UMIN: in getExpandedMinMaxOps()
1687 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
DLegalizeVectorOps.cpp333 case ISD::UMIN: in LegalizeOp()
DLegalizeVectorTypes.cpp116 case ISD::UMIN: in ScalarizeVectorResult()
694 case ISD::UMIN: in SplitVectorResult()
2097 case ISD::UMIN: in WidenVectorResult()
DSelectionDAG.cpp2463 case ISD::UMIN: in computeKnownBits()
2608 case ISD::UMIN: in ComputeNumSignBits()
3245 case ISD::UMIN: return std::make_pair(C1.ule(C2) ? C1 : C2, true); in FoldValue()
3528 case ISD::UMIN: in getNode()
DLegalizeDAG.cpp3131 case ISD::UMIN: in ExpandNode()
3140 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp227 setTargetDAGCombine(ISD::UMIN); in SITargetLowering()
2703 case ISD::UMIN: in minMaxOpcToMin3Max3Opc()
2810 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in performMinMaxCombine()
2873 case ISD::UMIN: in PerformDAGCombine()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp875 setOperationAction(ISD::UMIN, VT, Expand); in initActions()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp699 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2300 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9026 case ISD::UMIN: in tryMatchAcrossLaneShuffleForReduction()
9098 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine()
9132 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) || in performAcrossLaneMinMaxReductionCombine()
10127 ReplaceReductionResults(N, Results, DAG, ISD::UMIN, AArch64ISD::UMINV); in ReplaceNodeResults()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td403 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_from_tgsi.cpp801 NV50_IR_OPCODE_CASE(UMIN, MIN); in translateOpcode()

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