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Searched refs:UOps (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp55 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps() local
56 if (UOps) in getNumMicroOps()
57 return UOps; in getNumMicroOps()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps() local
80 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI); in getNumMicroOps()
DTargetInstrInfo.cpp1018 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps() local
1019 if (UOps >= 0) in getNumMicroOps()
1020 return UOps; in getNumMicroOps()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.cpp1983 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps() local
1984 if (UOps) in getNumMicroOps()
1985 return UOps; in getNumMicroOps()
2060 UOps = (NumRegs / 2); in getNumMicroOps()
2062 ++UOps; in getNumMicroOps()
2063 return UOps; in getNumMicroOps()
2065 UOps = (NumRegs / 2); in getNumMicroOps()
2071 ++UOps; in getNumMicroOps()
2072 return UOps; in getNumMicroOps()
2681 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; in getInstrLatency() local
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/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp2778 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt() local
2779 assert(UOps >= 0 && "bad # UOps"); in getNumMicroOpsSwiftLdSt()
2780 return UOps; in getNumMicroOpsSwiftLdSt()
3033 unsigned UOps = 1 + NumRegs; // 1 for address computation. in getNumMicroOpsSingleIssuePlusExtras() local
3059 ++UOps; // One for base register writeback. in getNumMicroOpsSingleIssuePlusExtras()
3064 UOps += 2; // One for base reg wb, one for write to pc. in getNumMicroOpsSingleIssuePlusExtras()
3067 return UOps; in getNumMicroOpsSingleIssuePlusExtras()
3163 unsigned UOps = (NumRegs / 2); in getNumMicroOps() local
3165 ++UOps; in getNumMicroOps()
3166 return UOps; in getNumMicroOps()
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