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Searched refs:VAR2 (Results 1 – 12 of 12) sorted by relevance

/external/arm-neon-tests/
Dstm-arm-neon-ref.h771 #define TEST_MACRO_64BITS_SIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2) \ argument
772 MACRO(VAR1, VAR2, , int, s, 8, 8); \
773 MACRO(VAR1, VAR2, , int, s, 16, 4); \
774 MACRO(VAR1, VAR2, , int, s, 32, 2); \
775 MACRO(VAR1, VAR2 , , int, s, 64, 1)
777 #define TEST_MACRO_64BITS_UNSIGNED_VARIANTS_2_5(MACRO, VAR1, VAR2) \ argument
778 MACRO(VAR1, VAR2, , uint, u, 8, 8); \
779 MACRO(VAR1, VAR2, , uint, u, 16, 4); \
780 MACRO(VAR1, VAR2, , uint, u, 32, 2); \
781 MACRO(VAR1, VAR2, , uint, u, 64, 1)
[all …]
/external/llvm/test/Transforms/InstCombine/
Dselect-cmp-cttz-ctlz.ll142 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i32
143 ; CHECK-NEXT: ret i32 [[VAR2]]
155 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i64
156 ; CHECK-NEXT: ret i64 [[VAR2]]
168 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i32 [[VAR1]] to i64
169 ; CHECK-NEXT: ret i64 [[VAR2]]
181 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i32
182 ; CHECK-NEXT: ret i32 [[VAR2]]
194 ; CHECK-NEXT: [[VAR2:%[a-zA-Z0-9]+]] = zext i16 [[VAR1]] to i64
195 ; CHECK-NEXT: ret i64 [[VAR2]]
[all …]
Dvec_shuffle.ll330 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <4 x i32> [[VAR1]], <4 x i32> undef, <4 x i32> <i3…
331 ; CHECK: ret <4 x i32> [[VAR2]]
355 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <4 x i32> [[VAR1]], <4 x i32> undef, <4 x i32> zer…
356 ; CHECK: ret <4 x i32> [[VAR2]]
382 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = shufflevector <8 x i16> [[VAR1]], <8 x i16> undef, <4 x i32> <i3…
383 ; CHECK: ret <4 x i16> [[VAR2]]
/external/llvm/test/CodeGen/PowerPC/
Dmcm-3.ll37 ; LARGE: .tc [[VAR2:[a-z0-9A-Z_.]+]][TC],[[VAR2]]
38 ; LARGE: .type [[VAR2]],@object
40 ; LARGE: .globl [[VAR2]]
41 ; LARGE: [[VAR2]]:
Dmcm-2.ll34 ; LARGE: .tc [[VAR2:[a-z0-9A-Z_.]+]][TC],[[VAR2]]
35 ; LARGE: .type [[VAR2]],@object
36 ; LARGE: .lcomm [[VAR2]],4,4
Dmcm-4.ll34 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
35 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
41 ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
42 ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
/external/clang/test/CodeGenCXX/
Dmangle-local-class-names.cpp30 SSSS VAR2(IVAR2); in FUNC() local
54 SSSS VAR2(IVAR2); in GORF() local
74 SSSS VAR2(x); in OmittingCode() local
/external/llvm/test/Transforms/IndVarSimplify/
Dloop_evaluate_1.ll27 ; CHECK: [[VAR2:%.+]] = lshr i32 [[VAR1]], 1
28 ; CHECK: [[VAR3:%.+]] = add i32 [[VAR2]], 1
/external/llvm/test/Transforms/LoopVectorize/
Dinduction-step.ll18 ; CHECK: %[[VAR2:.*]] = shufflevector <8 x i32> %[[VAR1]], <8 x i32> undef, <8 x i32> zeroinitiali…
19 ; CHECK: mul <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %[[VAR2]]
74 ; CHECK: %[[VAR2:.*]] = shufflevector <8 x i32> %[[VAR1]], <8 x i32> undef, <8 x i32> zeroinitiali…
75 ; CHECK: mul <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %[[VAR2]]
Dstore-shuffle-bug.ll23 ; CHECK: [[VAR2:%[a-zA-Z0-9.]+]] = load <4 x i32>
24 ; CHECK: [[VAR3:%[a-zA-Z0-9]+]] = add nsw <4 x i32> [[VAR2]], [[VAR1]]
/external/llvm/test/CodeGen/Hexagon/
Dextload-combine.ll40 ; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(##
41 ; CHECK: combine(#0, [[VAR2]])
/external/valgrind/drd/tests/
Dtsan_unittest.cpp5759 int VAR2 = 0; variable
5775 void Thread3() { CorrectWrite(&VAR2); } in Thread3()
5776 void Thread4() { WriteWhileHoldingReaderLock(&VAR2); } in Thread4()
5782 VAR2 = 0; in Run()
5784 ANNOTATE_TRACE_MEMORY(&VAR2); in Run()
5787 ANNOTATE_EXPECT_RACE_FOR_TSAN(&VAR2, "test122. TP. ReaderLock-ed while writing"); in Run()