| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 155 VREV64, // reverse elements within 64-bit doublewords enumerator
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| D | ARMISelLowering.cpp | 905 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4270 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
4367 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
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| D | ARMInstrNEON.td | 131 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
4683 // VREV64 : Vector Reverse elements within 64-bit doublewords
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vrev.ll | 151 ; vrev <4 x i16> should use VREV32 and not VREV64
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| /external/arm-neon-tests/ |
| D | ref-rvct-neon.txt | 3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
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| D | ref-rvct-neon-nofp16.txt | 3215 VREV64 output:
3216 VREV64:44:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3217 VREV64:45:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3218 VREV64:46:result_int32x2 [] = { fffffff1, fffffff0, }
3219 VREV64:47:result_int64x1 [] = { 3333333333333333, }
3220 VREV64:48:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3221 VREV64:49:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3222 VREV64:50:result_uint32x2 [] = { fffffff1, fffffff0, }
3223 VREV64:51:result_uint64x1 [] = { 3333333333333333, }
3224 VREV64:52:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
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| D | ref-rvct-all.txt | 3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
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| D | expected_input4gcc-nofp16.txt | 3062 VREV64 output:
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| D | expected_input4gcc.txt | 3270 VREV64 output:
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 153 VREV64, // reverse elements within 64-bit doublewords enumerator
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| D | ARMScheduleSwift.td | 549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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| D | ARMISelLowering.cpp | 1208 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4489 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6143 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
6206 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6269 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
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| D | ARMInstrNEON.td | 574 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
6264 // VREV64 : Vector Reverse elements within 64-bit doublewords
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 782 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",
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