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Searched refs:VT (Results 1 – 25 of 376) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1022 EVT VT = N->getValueType(0); in SelectTable() local
1037 ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, VT, Ops)); in SelectTable()
1044 EVT VT = LD->getMemoryVT(); in tryIndexedLoad() local
1056 if (VT == MVT::i64) in tryIndexedLoad()
1058 else if (VT == MVT::i32) { in tryIndexedLoad()
1070 } else if (VT == MVT::i16) { in tryIndexedLoad()
1083 } else if (VT == MVT::i8) { in tryIndexedLoad()
1096 } else if (VT == MVT::f16) { in tryIndexedLoad()
1098 } else if (VT == MVT::f32) { in tryIndexedLoad()
1100 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
[all …]
DAArch64ISelLowering.cpp212 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
213 setOperationAction(ISD::ROTL, VT, Expand); in AArch64TargetLowering()
214 setOperationAction(ISD::ROTR, VT, Expand); in AArch64TargetLowering()
227 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
228 setOperationAction(ISD::SDIVREM, VT, Expand); in AArch64TargetLowering()
229 setOperationAction(ISD::UDIVREM, VT, Expand); in AArch64TargetLowering()
419 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
420 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
421 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
422 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h167 virtual EVT getSetCCResultType(EVT VT) const;
202 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { in getRegClassFor() argument
203 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); in getRegClassFor()
204 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; in getRegClassFor()
214 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { in getRepRegClassFor() argument
215 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); in getRepRegClassFor()
216 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassFor()
222 virtual uint8_t getRepRegClassCostFor(EVT VT) const { in getRepRegClassCostFor() argument
223 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); in getRepRegClassCostFor()
224 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassCostFor()
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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h35 void DecodeInsertElementMask(MVT VT, unsigned Idx, unsigned Len,
46 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
48 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
50 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
54 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
56 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
61 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
66 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
71 void DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
[all …]
DX86ShuffleDecode.cpp48 void DecodeInsertElementMask(MVT VT, unsigned Idx, unsigned Len, in DecodeInsertElementMask() argument
50 unsigned NumElts = VT.getVectorNumElements(); in DecodeInsertElementMask()
77 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask() argument
78 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVSLDUPMask()
85 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask() argument
86 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVSHDUPMask()
93 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask() argument
94 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodeMOVDDUPMask()
95 unsigned ScalarSizeInBits = VT.getScalarSizeInBits(); in DecodeMOVDDUPMask()
96 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVDDUPMask()
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/external/llvm/include/llvm/Target/
DTargetLowering.h210 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction() argument
212 if (VT.getVectorNumElements() == 1) in getPreferredVectorAction()
237 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const { in isIntDivCheap() argument
323 virtual bool hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic() argument
379 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion() argument
385 EVT VT) const;
430 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() argument
431 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in getRegClassFor()
443 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor() argument
444 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
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/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h57 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
58 FastID(ID), VTs(VT), NumVTs(Num) {
461 SDVTList getVTList(EVT VT);
477 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
479 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
481 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
485 SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,
487 return getConstant(Val, DL, VT, true, isOpaque);
489 SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT,
491 return getConstant(Val, DL, VT, true, isOpaque);
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DValueTypes.h41 bool operator==(EVT VT) const {
42 return !(*this != VT);
44 bool operator!=(EVT VT) const {
45 if (V.SimpleTy != VT.V.SimpleTy)
48 return LLVMTy != VT.LLVMTy;
70 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) { in getVectorVT()
71 MVT M = MVT::getVectorVT(VT.V, NumElements); in getVectorVT()
74 return getExtendedVectorVT(Context, VT, NumElements); in getVectorVT()
194 bool bitsEq(EVT VT) const { in bitsEq()
195 if (EVT::operator==(VT)) return true; in bitsEq()
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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp79 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
81 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
86 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), in isValueValidForType()
679 EVT VT = N->getValueType(0); in VerifySDNode() local
681 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
686 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in VerifySDNode()
688 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
754 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
755 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
756 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
[all …]
DDAGCombiner.cpp343 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
352 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
503 bool isTypeLegal(const EVT &VT) { in isTypeLegal() argument
505 return TLI.isTypeLegal(VT); in isTypeLegal()
509 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
510 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
818 EVT VT = N0.getValueType(); in ReassociateOps() local
823 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R)) in ReassociateOps()
824 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in ReassociateOps()
830 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1); in ReassociateOps()
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DLegalizeVectorOps.cpp402 MVT VT = Op.getSimpleValueType(); in Promote() local
405 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); in Promote()
424 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
425 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); in Promote()
429 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in Promote()
435 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
447 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteINT_TO_FP()
471 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
476 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteFP_TO_INT()
[all …]
DTargetLowering.cpp150 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
154 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) in softenSetCCOperands()
163 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
164 (VT == MVT::f64) ? RTLIB::OEQ_F64 : in softenSetCCOperands()
165 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; in softenSetCCOperands()
169 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
170 (VT == MVT::f64) ? RTLIB::UNE_F64 : in softenSetCCOperands()
171 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; in softenSetCCOperands()
175 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
176 (VT == MVT::f64) ? RTLIB::OGE_F64 : in softenSetCCOperands()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp234 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
238 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
298 bool isTypeLegal(const EVT &VT) { in isTypeLegal() argument
300 return TLI.isTypeLegal(VT); in isTypeLegal()
533 EVT VT = N0.getValueType(); in ReassociateOps() local
538 DAG.FoldConstantArithmetic(Opc, VT, in ReassociateOps()
541 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in ReassociateOps()
545 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, in ReassociateOps()
548 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); in ReassociateOps()
556 DAG.FoldConstantArithmetic(Opc, VT, in ReassociateOps()
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DSelectionDAG.cpp63 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { in EVTToAPFloatSemantics() argument
64 switch (VT.getSimpleVT().SimpleTy) { in EVTToAPFloatSemantics()
88 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
90 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
93 if (VT == MVT::ppcf128 || in isValueValidForType()
100 (void) Val2.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, in isValueValidForType()
633 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
634 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
635 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
637 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0; in RemoveNodeFromCSEMaps()
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DLegalizeVectorOps.cpp246 EVT VT = Op.getValueType(); in PromoteVectorOp() local
249 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); in PromoteVectorOp()
262 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in PromoteVectorOp()
268 EVT VT = Op.getOperand(0).getValueType(); in ExpandVSELECT() local
277 if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) || in ExpandVSELECT()
278 !TLI.isOperationLegalOrCustom(ISD::XOR, VT) || in ExpandVSELECT()
279 !TLI.isOperationLegalOrCustom(ISD::OR, VT)) in ExpandVSELECT()
282 assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits() in ExpandVSELECT()
287 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); in ExpandVSELECT()
288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
[all …]
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp75 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
93 MVT VT = Outs[i].VT; in CheckReturn() local
95 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
107 MVT VT = Outs[i].VT; in AnalyzeReturn() local
109 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeReturn()
112 << EVT(VT).getEVTString() << '\n'; in AnalyzeReturn()
125 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
162 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
165 << EVT(VT).getEVTString() << '\n'; in AnalyzeCallResult()
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/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_format.c50 #define VT(pipe, fmt, rbfmt, swapfmt) \ macro
81 VT(R8_UNORM, 8_UNORM, R8_UNORM, WZYX),
82 VT(R8_SNORM, 8_SNORM, R8_SNORM, WZYX),
83 VT(R8_UINT, 8_UINT, R8_UINT, WZYX),
84 VT(R8_SINT, 8_SINT, R8_SINT, WZYX),
102 VT(R16_UNORM, 16_UNORM, R16_UNORM, WZYX),
103 VT(R16_SNORM, 16_SNORM, R16_SNORM, WZYX),
104 VT(R16_UINT, 16_UINT, R16_UINT, WZYX),
105 VT(R16_SINT, 16_SINT, R16_SINT, WZYX),
108 VT(R16_FLOAT, 16_FLOAT, R16_FLOAT, WZYX),
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
50 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) { in getEquivalentBitType() argument
59 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentBitType()
100 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
101 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
102 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
103 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
106 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
107 if (VT == MVT::i64) in AMDGPUTargetLowering()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DCallingConvLower.cpp74 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
92 MVT VT = Outs[i].VT; in CheckReturn() local
94 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
106 MVT VT = Outs[i].VT; in AnalyzeReturn() local
108 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeReturn()
111 << EVT(VT).getEVTString(); in AnalyzeReturn()
124 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
162 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
165 << EVT(VT).getEVTString() << "\n"; in AnalyzeCallResult()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h316 SDVTList getVTList(EVT VT);
325 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
326 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
327 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
329 SDValue getTargetConstant(uint64_t Val, EVT VT) {
330 return getConstant(Val, VT, true);
332 SDValue getTargetConstant(const APInt &Val, EVT VT) {
333 return getConstant(Val, VT, true);
335 SDValue getTargetConstant(const ConstantInt &Val, EVT VT) {
336 return getConstant(Val, VT, true);
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/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_format.c48 #define VT(pipe, fmt, rbfmt, swapfmt) \ macro
79 VT(R8_UNORM, 8_UNORM, R8_UNORM, WZYX),
81 VT(R8_UINT, 8_UINT, R8_UINT, WZYX),
82 VT(R8_SINT, 8_SINT, R8_SINT, WZYX),
100 VT(R16_UNORM, 16_UNORM, R16_UNORM, WZYX),
101 VT(R16_SNORM, 16_SNORM, R16_SNORM, WZYX),
102 VT(R16_UINT, 16_UINT, R16_UINT, WZYX),
103 VT(R16_SINT, 16_SINT, R16_SINT, WZYX),
106 VT(R16_FLOAT, 16_FLOAT, R16_FLOAT, WZYX),
121 VT(R8G8_UNORM, 8_8_UNORM, R8G8_UNORM, WZYX),
[all …]
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_format.c45 #define VT(pipe, fmt, rbfmt, swapfmt) \ macro
76 VT(R8_UNORM, 8_UNORM, R8_UNORM, WZYX),
77 VT(R8_SNORM, 8_SNORM, NONE, WZYX),
78 VT(R8_UINT, 8_UINT, R8_UINT, WZYX),
79 VT(R8_SINT, 8_SINT, R8_SINT, WZYX),
97 VT(R16_UNORM, 16_UNORM, NONE, WZYX),
98 VT(R16_SNORM, 16_SNORM, NONE, WZYX),
99 VT(R16_UINT, 16_UINT, R16_UINT, WZYX),
100 VT(R16_SINT, 16_SINT, R16_SINT, WZYX),
103 VT(R16_FLOAT, 16_FLOAT, R16_FLOAT,WZYX),
[all …]
/external/clang/test/SemaCXX/
Dcxx11-call-to-deleted-constructor.cpp10 template <class VT, unsigned int ROWS = 0, unsigned int COLS = 0>
14 typedef VT value_type;
18 template <class VT, unsigned int SIZE> using Vector = Matrix<VT, SIZE, 1>;
20 template <class VT>
21 using RGBValue = Vector<VT, 3>;
24 template <class VT> class Matrix<VT, 0, 0> { // expected-note {{passing argument to parameter here}}
26 typedef VT value_type;
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp141 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
282 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) { in X86TargetLowering()
283 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
284 setOperationAction(ISD::MULHU, VT, Expand); in X86TargetLowering()
285 setOperationAction(ISD::SDIV, VT, Expand); in X86TargetLowering()
286 setOperationAction(ISD::UDIV, VT, Expand); in X86TargetLowering()
287 setOperationAction(ISD::SREM, VT, Expand); in X86TargetLowering()
288 setOperationAction(ISD::UREM, VT, Expand); in X86TargetLowering()
291 setOperationAction(ISD::ADDC, VT, Custom); in X86TargetLowering()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
84 EVT VT = Vec.getValueType(); in Extract128BitVector() local
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); in Extract128BitVector()
86 EVT ElVT = VT.getVectorElementType(); in Extract128BitVector()
87 int Factor = VT.getSizeInBits()/128; in Extract128BitVector()
89 VT.getVectorNumElements()/Factor); in Extract128BitVector()
128 EVT VT = Vec.getValueType(); in Insert128BitVector() local
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); in Insert128BitVector()
131 EVT ElVT = VT.getVectorElementType(); in Insert128BitVector()
352 MVT VT = IntVTs[i]; in X86TargetLowering() local
[all …]

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