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Searched refs:ValueVT (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp321 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
326 ValueVT = MVT::i32; in SelectIndexedLoad()
330 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
342 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
543 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
588 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
999 EVT ValueVT = N->getValueType(0); in SelectBitOp() local
1002 if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 || in SelectBitOp()
1003 ValueVT == MVT::f32 || ValueVT == MVT::f64)) { in SelectBitOp()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp90 EVT PartVT, EVT ValueVT);
99 unsigned NumParts, EVT PartVT, EVT ValueVT, in getCopyFromParts() argument
101 if (ValueVT.isVector()) in getCopyFromParts()
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); in getCopyFromParts()
110 if (ValueVT.isInteger()) { in getCopyFromParts()
112 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && in getCopyFromParts()
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && in getCopyFromParts()
[all …]
DFunctionLoweringInfo.cpp225 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
226 EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
228 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp121 MVT PartVT, EVT ValueVT, const Value *V);
130 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
132 if (ValueVT.isVector()) in getCopyFromParts()
134 PartVT, ValueVT, V); in getCopyFromParts()
142 if (ValueVT.isInteger()) { in getCopyFromParts()
144 unsigned ValueBits = ValueVT.getSizeInBits(); in getCopyFromParts()
151 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
193 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
198 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in getCopyFromParts()
200 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
DLegalizeTypesGeneric.cpp261 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
262 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
292 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
476 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
477 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
491 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
DFunctionLoweringInfo.cpp384 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
385 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
387 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1361 EVT ValueVT = Value.getValueType(); in LowerSTORE() local
1364 ValueVT.isVector()) { in LowerSTORE()
1407 ValueVT.bitsGE(MVT::i32)) { in LowerSTORE()
1436 if (ValueVT.isVector()) { in LowerSTORE()
1437 unsigned NumElemVT = ValueVT.getVectorNumElements(); in LowerSTORE()
1438 EVT ElemVT = ValueVT.getVectorElementType(); in LowerSTORE()
1458 if (ValueVT == MVT::i8) { in LowerSTORE()