| /external/pcre/dist2/doc/ |
| D | pcre2-config.txt | 27 --prefix Writes the directory prefix used in the PCRE2 installation
32 Writes the directory prefix used in the PCRE2 installation
36 --version Writes the version number of the installed PCRE2 libraries to
39 --libs8 Writes to the standard output the command line options
43 --libs16 Writes to the standard output the command line options
47 --libs32 Writes to the standard output the command line options
52 Writes to the standard output the command line options
56 --cflags Writes to the standard output the command line options
61 Writes to the standard output the command line options
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 383 IdxVec &Writes, IdxVec &Reads) const { in findRWs() argument
387 findRWs(WriteDefs, Writes, false); in findRWs()
509 IdxVec Writes, Reads; in collectSchedClasses() local
511 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
516 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses()
551 if (!SC.Writes.empty()) { in collectSchedClasses()
554 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI) in collectSchedClasses()
567 IdxVec Writes; in collectSchedClasses() local
570 Writes, Reads); in collectSchedClasses()
571 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) in collectSchedClasses()
[all …]
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| D | CodeGenSchedule.h | 132 IdxVec Writes; member
148 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
370 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
382 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes,
432 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| D | SubtargetEmitter.cpp | 852 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
866 Writes.clear(); in GenSchedClassTables()
869 Writes, Reads); in GenSchedClassTables()
872 if (Writes.empty()) { in GenSchedClassTables()
879 Writes, Reads); in GenSchedClassTables()
883 if (Writes.empty()) { in GenSchedClassTables()
893 for (unsigned W : Writes) { in GenSchedClassTables()
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| /external/blktrace/doc/ |
| D | blktrace.tex | 163 Reads Queued: 0, 0KiB Writes Queued: 7, 128KiB
165 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
170 Reads Queued: 0, 0KiB Writes Queued: 1, 28KiB
172 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
177 Reads Queued: 0, 0KiB Writes Queued: 11, 168KiB
179 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
299 Reads Queued: 0, 0KiB Writes Queued: 9, 5,520KiB
301 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
305 Reads Queued: 2,411, 38,576KiB Writes Queued: 769, 425,408KiB
307 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
[all …]
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| /external/swiftshader/third_party/LLVM/bindings/ocaml/bitwriter/ |
| D | llvm_bitwriter.ml | 16 (* Writes the bitcode for module the given path. Returns true if successful. *)
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | InlineSpiller.cpp | 866 bool Reads, Writes; in reMaterializeFor() local
868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops); in reMaterializeFor()
869 if (Writes) { in reMaterializeFor()
1126 bool Reads, Writes; in spillAroundUses() local
1128 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops); in spillAroundUses()
1146 if (Writes) { in spillAroundUses()
1190 if (Writes) { in spillAroundUses()
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| D | RegisterCoalescer.cpp | 942 bool Reads, Writes; in UpdateRegDefsUses() local
943 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); in UpdateRegDefsUses()
975 else if (!Reads && Writes) in UpdateRegDefsUses()
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| /external/mockito/src/main/java/org/mockito/internal/util/concurrent/ |
| D | README.md | 9 This map does not implement the `java.util.Map` interface to simplify the implementation. Writes to…
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 1883 list <WriteSequence> Writes = writes;
2087 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2088 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2089 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2090 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2091 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2092 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2093 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2094 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2192 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBundle.h | 158 bool Writes; member
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| /external/deqp/doc/testspecs/GLES31/ |
| D | functional.ssbo.txt | 60 shader text. Writes are validated by reading back the SSBO and comparing
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstrBundle.cpp | 286 RI.Writes = true; in analyzeVirtReg()
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| D | InlineSpiller.cpp | 925 if (RI.Writes) { in spillAroundUses()
967 if (RI.Writes) in spillAroundUses()
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| D | MachinePipeliner.cpp | 3651 bool Reads, Writes; in orderDependence() local
3652 std::tie(Reads, Writes) = in orderDependence()
3661 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
3669 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
3676 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
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| D | RegisterCoalescer.cpp | 1276 bool Reads, Writes; in updateRegDefsUses() local
1277 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); in updateRegDefsUses()
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| /external/python/cpython2/Doc/library/ |
| D | gdbm.rst | 63 | ``'f'`` | Open the database in fast mode. Writes |
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| D | basehttpserver.rst | 216 Writes a specific HTTP header to the output stream. *keyword* should
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| D | xml.etree.elementtree.rst | 450 Writes an element tree or element structure to sys.stdout. This function
855 Writes the element tree to a file, as XML. *file* is a file name, or a
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| D | codecs.rst | 590 Writes the object's contents encoded to the stream.
595 Writes the concatenated list of strings to the stream (possibly by reusing
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| D | _winreg.rst | 213 Writes all the attributes of a key to the registry.
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| D | cgi.rst | 328 Robust test CGI script, usable as main program. Writes minimal HTTP headers and
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| /external/nanopb-c/docs/ |
| D | reference.rst | 395 Writes data to an output stream. Always use this function, instead of trying to call stream callbac…
494 Writes the length of a string as varint and then contents of the string. Works for fields of type `…
505 Writes 4 bytes to stream and swaps bytes on big-endian architectures. Works for fields of type `fix…
515 Writes 8 bytes to stream and swaps bytes on big-endian architecture. Works for fields of type `fixe…
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| /external/llvm/include/llvm/Target/ |
| D | TargetSchedule.td | 240 list<SchedWrite> Writes = writes;
324 // to implement pipeline bypass. The Writes list may be empty to
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| /external/icu/icu4c/source/data/mappings/ |
| D | convrtrs.txt | 247 # From Unicode: Writes BOM.
258 # From Unicode: Writes BOM.
271 # From Unicode: Writes BOM.
|