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1 /*
2  * cpufeature.h
3  *
4  * Defines x86 CPU feature bits
5  */
6 
7 #ifndef __ASM_I386_CPUFEATURE_H
8 #define __ASM_I386_CPUFEATURE_H
9 
10 #define NCAPINTS	9	/* N 32-bit words worth of info */
11 
12 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
13 #define X86_FEATURE_FPU		(0*32+ 0)	/* Onboard FPU */
14 #define X86_FEATURE_VME		(0*32+ 1)	/* Virtual Mode Extensions */
15 #define X86_FEATURE_DE		(0*32+ 2)	/* Debugging Extensions */
16 #define X86_FEATURE_PSE 	(0*32+ 3)	/* Page Size Extensions */
17 #define X86_FEATURE_TSC		(0*32+ 4)	/* Time Stamp Counter */
18 #define X86_FEATURE_MSR		(0*32+ 5)	/* Model-Specific Registers, RDMSR, WRMSR */
19 #define X86_FEATURE_PAE		(0*32+ 6)	/* Physical Address Extensions */
20 #define X86_FEATURE_MCE		(0*32+ 7)	/* Machine Check Architecture */
21 #define X86_FEATURE_CX8		(0*32+ 8)	/* CMPXCHG8 instruction */
22 #define X86_FEATURE_APIC	(0*32+ 9)	/* Onboard APIC */
23 #define X86_FEATURE_SEP		(0*32+11)	/* SYSENTER/SYSEXIT */
24 #define X86_FEATURE_MTRR	(0*32+12)	/* Memory Type Range Registers */
25 #define X86_FEATURE_PGE		(0*32+13)	/* Page Global Enable */
26 #define X86_FEATURE_MCA		(0*32+14)	/* Machine Check Architecture */
27 #define X86_FEATURE_CMOV	(0*32+15)	/* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
28 #define X86_FEATURE_PAT		(0*32+16)	/* Page Attribute Table */
29 #define X86_FEATURE_PSE36	(0*32+17)	/* 36-bit PSEs */
30 #define X86_FEATURE_PN		(0*32+18)	/* Processor serial number */
31 #define X86_FEATURE_CLFLSH	(0*32+19)	/* Supports the CLFLUSH instruction */
32 #define X86_FEATURE_DTES	(0*32+21)	/* Debug Trace Store */
33 #define X86_FEATURE_ACPI	(0*32+22)	/* ACPI via MSR */
34 #define X86_FEATURE_MMX		(0*32+23)	/* Multimedia Extensions */
35 #define X86_FEATURE_FXSR	(0*32+24)	/* FXSAVE and FXRSTOR instructions (fast save and restore */
36 					  /* of FPU context), and CR4.OSFXSR available */
37 #define X86_FEATURE_XMM		(0*32+25)	/* Streaming SIMD Extensions */
38 #define X86_FEATURE_XMM2	(0*32+26)	/* Streaming SIMD Extensions-2 */
39 #define X86_FEATURE_SELFSNOOP	(0*32+27)	/* CPU self snoop */
40 #define X86_FEATURE_HT		(0*32+28)	/* Hyper-Threading */
41 #define X86_FEATURE_ACC		(0*32+29)	/* Automatic clock control */
42 #define X86_FEATURE_IA64	(0*32+30)	/* IA-64 processor */
43 #define X86_FEATURE_PBE         (0*32+31)	/* Pending Break Enable */
44 
45 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
46 /* Don't duplicate feature flags which are redundant with Intel! */
47 #define X86_FEATURE_SYSCALL	(1*32+11)	/* SYSCALL/SYSRET */
48 #define X86_FEATURE_MP		(1*32+19)	/* MP Capable. */
49 #define X86_FEATURE_NX		(1*32+20)	/* Execute Disable */
50 #define X86_FEATURE_MMXEXT	(1*32+22)	/* AMD MMX extensions */
51 #define X86_FEATURE_FXSR_OPT    (1*32+25)	/* FXSAVE/FXRSTOR optimizations */
52 #define X86_FEATURE_GBPAGES     (1*32+26)	/* "pdpe1gb" GB pages */
53 #define X86_FEATURE_RDTSCP      (1*32+27)	/* RDTSCP */
54 #define X86_FEATURE_LM		(1*32+29)	/* Long Mode (x86-64) */
55 #define X86_FEATURE_3DNOWEXT	(1*32+30)	/* AMD 3DNow! extensions */
56 #define X86_FEATURE_3DNOW	(1*32+31)	/* 3DNow! */
57 
58 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
59 #define X86_FEATURE_RECOVERY	(2*32+ 0)	/* CPU in recovery mode */
60 #define X86_FEATURE_LONGRUN	(2*32+ 1)	/* Longrun power control */
61 #define X86_FEATURE_LRTI	(2*32+ 3)	/* LongRun table interface */
62 
63 /* Other features, Linux-defined mapping, word 3 */
64 /* This range is used for feature bits which conflict or are synthesized */
65 #define X86_FEATURE_CXMMX	(3*32+ 0)	/* Cyrix MMX extensions */
66 #define X86_FEATURE_K6_MTRR	(3*32+ 1)	/* AMD K6 nonstandard MTRRs */
67 #define X86_FEATURE_CYRIX_ARR	(3*32+ 2)	/* Cyrix ARRs (= MTRRs) */
68 #define X86_FEATURE_CENTAUR_MCR	(3*32+ 3)	/* Centaur MCRs (= MTRRs) */
69 /* cpu types for specific tunings: */
70 #define X86_FEATURE_K8		(3*32+ 4)	/* Opteron, Athlon64 */
71 #define X86_FEATURE_K7		(3*32+ 5)	/* Athlon */
72 #define X86_FEATURE_P3		(3*32+ 6)	/* P3 */
73 #define X86_FEATURE_P4		(3*32+ 7)	/* P4 */
74 
75 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
76 #define X86_FEATURE_XMM3	(4*32+ 0)	/* Streaming SIMD Extensions-3 */
77 #define X86_FEATURE_PCLMULQDQ   (4*32+ 1)	/* PCLMULQDQ instruction */
78 #define X86_FEATURE_DTES64      (4*32+ 2)	/* 64-bit Debug Store */
79 #define X86_FEATURE_MWAIT	(4*32+ 3)	/* Monitor/Mwait support */
80 #define X86_FEATURE_DSCPL	(4*32+ 4)	/* CPL Qualified Debug Store */
81 #define X86_FEATURE_VMX		(4*32+ 5)	/* Hardware virtualization */
82 #define X86_FEATURE_SMX         (4*32+ 6)	/* Safer mode */
83 #define X86_FEATURE_EST		(4*32+ 7)	/* Enhanced SpeedStep */
84 #define X86_FEATURE_TM2		(4*32+ 8)	/* Thermal Monitor 2 */
85 #define X86_FEATURE_SSE3        (4*32+ 9)	/* Supplemental SSE-3 */
86 #define X86_FEATURE_CID		(4*32+10)	/* Context ID */
87 #define X86_FEATURE_FMA         (4*32+12)	/* Fused multiply-add */
88 #define X86_FEATURE_CX16        (4*32+13)	/* CMPXCHG16B */
89 #define X86_FEATURE_XTPR	(4*32+14)	/* Send Task Priority Messages */
90 #define X86_FEATURE_PDCM        (4*32+15)	/* Performance Capabilities */
91 #define X86_FEATURE_DCA         (4*32+18)	/* Direct Cache Access */
92 #define X86_FEATURE_XMM4_1      (4*32+19)	/* "sse4_1" SSE-4.1 */
93 #define X86_FEATURE_XMM4_2      (4*32+20)	/* "sse4_2" SSE-4.2 */
94 #define X86_FEATURE_X2APIC      (4*32+21)	/* x2APIC */
95 #define X86_FEATURE_MOVBE       (4*32+22)	/* MOVBE instruction */
96 #define X86_FEATURE_POPCNT      (4*32+23)	/* POPCNT instruction */
97 #define X86_FEATURE_AES         (4*32+25)	/* AES instructions */
98 #define X86_FEATURE_XSAVE       (4*32+26)	/* XSAVE/XRSTOR/XSETBV/XGETBV */
99 #define X86_FEATURE_OSXSAVE     (4*32+27)	/* "" XSAVE enabled in the OS */
100 #define X86_FEATURE_AVX         (4*32+28)	/* Advanced Vector Extensions */
101 #define X86_FEATURE_HYPERVISOR  (4*32+31)	/* Running on a hypervisor */
102 
103 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
104 #define X86_FEATURE_XSTORE	(5*32+ 2)	/* on-CPU RNG present (xstore insn) */
105 #define X86_FEATURE_XSTORE_EN	(5*32+ 3)	/* on-CPU RNG enabled */
106 #define X86_FEATURE_XCRYPT	(5*32+ 6)	/* on-CPU crypto (xcrypt insn) */
107 #define X86_FEATURE_XCRYPT_EN	(5*32+ 7)	/* on-CPU crypto enabled */
108 #define X86_FEATURE_ACE2        (5*32+ 8)	/* Advanced Cryptography Engine v2 */
109 #define X86_FEATURE_ACE2_EN     (5*32+ 9)	/* ACE v2 enabled */
110 #define X86_FEATURE_PHE         (5*32+10)	/* PadLock Hash Engine */
111 #define X86_FEATURE_PHE_EN      (5*32+11)	/* PHE enabled */
112 #define X86_FEATURE_PMM         (5*32+12)	/* PadLock Montgomery Multiplier */
113 #define X86_FEATURE_PMM_EN      (5*32+13)	/* PMM enabled */
114 
115 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
116 #define X86_FEATURE_LAHF_LM	(6*32+ 0)	/* LAHF/SAHF in long mode */
117 #define X86_FEATURE_CMP_LEGACY	(6*32+ 1)	/* If yes HyperThreading not valid */
118 #define X86_FEATURE_SVM		(6*32+ 2)	/* Secure virtual machine */
119 #define X86_FEATURE_EXTAPIC     (6*32+ 3)	/* Extended APIC space */
120 #define X86_FEATURE_CR8_LEGACY  (6*32+ 4)	/* CR8 in 32-bit mode */
121 #define X86_FEATURE_ABM         (6*32+ 5)	/* Advanced bit manipulation */
122 #define X86_FEATURE_SSE4A       (6*32+ 6)	/* SSE-4A */
123 #define X86_FEATURE_MISALIGNSSE (6*32+ 7)	/* Misaligned SSE mode */
124 #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8)	/* 3DNow prefetch instructions */
125 #define X86_FEATURE_OSVW        (6*32+ 9)	/* OS Visible Workaround */
126 #define X86_FEATURE_IBS         (6*32+10)	/* Instruction Based Sampling */
127 #define X86_FEATURE_SSE5        (6*32+11)	/* SSE-5 */
128 #define X86_FEATURE_SKINIT      (6*32+12)	/* SKINIT/STGI instructions */
129 #define X86_FEATURE_WDT         (6*32+13)	/* Watchdog timer */
130 
131 /*
132  *  * Auxiliary flags: Linux defined - For features scattered in various
133  *   * CPUID levels like 0x6, 0xA etc
134  *    */
135 #define X86_FEATURE_IDA         (7*32+ 0)	/* Intel Dynamic Acceleration */
136 #define X86_FEATURE_ARAT        (7*32+ 1)	/* Always Running APIC Timer */
137 
138 /* Virtualization flags: Linux defined */
139 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0)	/* Intel TPR Shadow */
140 #define X86_FEATURE_VNMI        (8*32+ 1)	/* Intel Virtual NMI */
141 #define X86_FEATURE_FLEXPRIORITY (8*32+ 2)	/* Intel FlexPriority */
142 #define X86_FEATURE_EPT         (8*32+ 3)	/* Intel Extended Page Table */
143 #define X86_FEATURE_VPID        (8*32+ 4)	/* Intel Virtual Processor ID */
144 
145 #endif /* __ASM_I386_CPUFEATURE_H */
146 
147 /*
148  * Local Variables:
149  * mode:c
150  * comment-column:42
151  * End:
152  */
153