1 /*
2 * Definitions for the new Marvell Yukon / SysKonnect driver.
3 */
4 #ifndef _SKGE_H
5 #define _SKGE_H
6
7 FILE_LICENCE ( GPL2_ONLY );
8
9 /* PCI config registers */
10 #define PCI_DEV_REG1 0x40
11 #define PCI_PHY_COMA 0x8000000
12 #define PCI_VIO 0x2000000
13
14 #define PCI_DEV_REG2 0x44
15 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
16 #define PCI_REV_DESC 1<<2 /* Reverse Descriptor bytes */
17
18 #define DRV_NAME "skge"
19 #define DRV_VERSION "1.13"
20 #define PFX DRV_NAME " "
21
22 #define NUM_TX_DESC 8
23 #define NUM_RX_DESC 8
24
25 /* mdeck used a 16 byte alignment, but datasheet says 8 bytes is sufficient */
26 #define SKGE_RING_ALIGN 8
27 #define RX_BUF_SIZE 1536
28 #define PHY_RETRIES 1000
29
30 #define TX_RING_SIZE ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) )
31 #define RX_RING_SIZE ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) )
32 #define RING_SIZE ( TX_RING_SIZE + RX_RING_SIZE )
33
34 #define SKGE_REG_SIZE 0x4000
35
36 #define SKGE_EEPROM_MAGIC 0x9933aabb
37
38 /* Added for gPXE ------------------ */
39
40 /* from ethtool.h */
41 #define AUTONEG_DISABLE 0x00
42 #define AUTONEG_ENABLE 0x01
43
44 #define DUPLEX_HALF 0x00
45 #define DUPLEX_FULL 0x01
46
47 #define SPEED_10 10
48 #define SPEED_100 100
49 #define SPEED_1000 1000
50
51 #define ADVERTISED_10baseT_Half (1 << 0)
52 #define ADVERTISED_10baseT_Full (1 << 1)
53 #define ADVERTISED_100baseT_Half (1 << 2)
54 #define ADVERTISED_100baseT_Full (1 << 3)
55 #define ADVERTISED_1000baseT_Half (1 << 4)
56 #define ADVERTISED_1000baseT_Full (1 << 5)
57
58 #define SUPPORTED_10baseT_Half (1 << 0)
59 #define SUPPORTED_10baseT_Full (1 << 1)
60 #define SUPPORTED_100baseT_Half (1 << 2)
61 #define SUPPORTED_100baseT_Full (1 << 3)
62 #define SUPPORTED_1000baseT_Half (1 << 4)
63 #define SUPPORTED_1000baseT_Full (1 << 5)
64 #define SUPPORTED_Autoneg (1 << 6)
65 #define SUPPORTED_TP (1 << 7)
66 #define SUPPORTED_FIBRE (1 << 10)
67
68 /* from kernel.h */
69 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
70
71 /* ----------------------------------- */
72
73 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
74 PCI_STATUS_SIG_SYSTEM_ERROR | \
75 PCI_STATUS_REC_MASTER_ABORT | \
76 PCI_STATUS_REC_TARGET_ABORT | \
77 PCI_STATUS_PARITY)
78
79 enum csr_regs {
80 B0_RAP = 0x0000,
81 B0_CTST = 0x0004,
82 B0_LED = 0x0006,
83 B0_POWER_CTRL = 0x0007,
84 B0_ISRC = 0x0008,
85 B0_IMSK = 0x000c,
86 B0_HWE_ISRC = 0x0010,
87 B0_HWE_IMSK = 0x0014,
88 B0_SP_ISRC = 0x0018,
89 B0_XM1_IMSK = 0x0020,
90 B0_XM1_ISRC = 0x0028,
91 B0_XM1_PHY_ADDR = 0x0030,
92 B0_XM1_PHY_DATA = 0x0034,
93 B0_XM2_IMSK = 0x0040,
94 B0_XM2_ISRC = 0x0048,
95 B0_XM2_PHY_ADDR = 0x0050,
96 B0_XM2_PHY_DATA = 0x0054,
97 B0_R1_CSR = 0x0060,
98 B0_R2_CSR = 0x0064,
99 B0_XS1_CSR = 0x0068,
100 B0_XA1_CSR = 0x006c,
101 B0_XS2_CSR = 0x0070,
102 B0_XA2_CSR = 0x0074,
103
104 B2_MAC_1 = 0x0100,
105 B2_MAC_2 = 0x0108,
106 B2_MAC_3 = 0x0110,
107 B2_CONN_TYP = 0x0118,
108 B2_PMD_TYP = 0x0119,
109 B2_MAC_CFG = 0x011a,
110 B2_CHIP_ID = 0x011b,
111 B2_E_0 = 0x011c,
112 B2_E_1 = 0x011d,
113 B2_E_2 = 0x011e,
114 B2_E_3 = 0x011f,
115 B2_FAR = 0x0120,
116 B2_FDP = 0x0124,
117 B2_LD_CTRL = 0x0128,
118 B2_LD_TEST = 0x0129,
119 B2_TI_INI = 0x0130,
120 B2_TI_VAL = 0x0134,
121 B2_TI_CTRL = 0x0138,
122 B2_TI_TEST = 0x0139,
123 B2_IRQM_INI = 0x0140,
124 B2_IRQM_VAL = 0x0144,
125 B2_IRQM_CTRL = 0x0148,
126 B2_IRQM_TEST = 0x0149,
127 B2_IRQM_MSK = 0x014c,
128 B2_IRQM_HWE_MSK = 0x0150,
129 B2_TST_CTRL1 = 0x0158,
130 B2_TST_CTRL2 = 0x0159,
131 B2_GP_IO = 0x015c,
132 B2_I2C_CTRL = 0x0160,
133 B2_I2C_DATA = 0x0164,
134 B2_I2C_IRQ = 0x0168,
135 B2_I2C_SW = 0x016c,
136 B2_BSC_INI = 0x0170,
137 B2_BSC_VAL = 0x0174,
138 B2_BSC_CTRL = 0x0178,
139 B2_BSC_STAT = 0x0179,
140 B2_BSC_TST = 0x017a,
141
142 B3_RAM_ADDR = 0x0180,
143 B3_RAM_DATA_LO = 0x0184,
144 B3_RAM_DATA_HI = 0x0188,
145 B3_RI_WTO_R1 = 0x0190,
146 B3_RI_WTO_XA1 = 0x0191,
147 B3_RI_WTO_XS1 = 0x0192,
148 B3_RI_RTO_R1 = 0x0193,
149 B3_RI_RTO_XA1 = 0x0194,
150 B3_RI_RTO_XS1 = 0x0195,
151 B3_RI_WTO_R2 = 0x0196,
152 B3_RI_WTO_XA2 = 0x0197,
153 B3_RI_WTO_XS2 = 0x0198,
154 B3_RI_RTO_R2 = 0x0199,
155 B3_RI_RTO_XA2 = 0x019a,
156 B3_RI_RTO_XS2 = 0x019b,
157 B3_RI_TO_VAL = 0x019c,
158 B3_RI_CTRL = 0x01a0,
159 B3_RI_TEST = 0x01a2,
160 B3_MA_TOINI_RX1 = 0x01b0,
161 B3_MA_TOINI_RX2 = 0x01b1,
162 B3_MA_TOINI_TX1 = 0x01b2,
163 B3_MA_TOINI_TX2 = 0x01b3,
164 B3_MA_TOVAL_RX1 = 0x01b4,
165 B3_MA_TOVAL_RX2 = 0x01b5,
166 B3_MA_TOVAL_TX1 = 0x01b6,
167 B3_MA_TOVAL_TX2 = 0x01b7,
168 B3_MA_TO_CTRL = 0x01b8,
169 B3_MA_TO_TEST = 0x01ba,
170 B3_MA_RCINI_RX1 = 0x01c0,
171 B3_MA_RCINI_RX2 = 0x01c1,
172 B3_MA_RCINI_TX1 = 0x01c2,
173 B3_MA_RCINI_TX2 = 0x01c3,
174 B3_MA_RCVAL_RX1 = 0x01c4,
175 B3_MA_RCVAL_RX2 = 0x01c5,
176 B3_MA_RCVAL_TX1 = 0x01c6,
177 B3_MA_RCVAL_TX2 = 0x01c7,
178 B3_MA_RC_CTRL = 0x01c8,
179 B3_MA_RC_TEST = 0x01ca,
180 B3_PA_TOINI_RX1 = 0x01d0,
181 B3_PA_TOINI_RX2 = 0x01d4,
182 B3_PA_TOINI_TX1 = 0x01d8,
183 B3_PA_TOINI_TX2 = 0x01dc,
184 B3_PA_TOVAL_RX1 = 0x01e0,
185 B3_PA_TOVAL_RX2 = 0x01e4,
186 B3_PA_TOVAL_TX1 = 0x01e8,
187 B3_PA_TOVAL_TX2 = 0x01ec,
188 B3_PA_CTRL = 0x01f0,
189 B3_PA_TEST = 0x01f2,
190 };
191
192 /* B0_CTST 16 bit Control/Status register */
193 enum {
194 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
195 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
196 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
197 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
198 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
199 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
200 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
201 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
202 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
203 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
204 CS_MRST_CLR = 1<<3, /* Clear Master reset */
205 CS_MRST_SET = 1<<2, /* Set Master reset */
206 CS_RST_CLR = 1<<1, /* Clear Software reset */
207 CS_RST_SET = 1, /* Set Software reset */
208
209 /* B0_LED 8 Bit LED register */
210 /* Bit 7.. 2: reserved */
211 LED_STAT_ON = 1<<1, /* Status LED on */
212 LED_STAT_OFF = 1, /* Status LED off */
213
214 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
215 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
216 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
217 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
218 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
219 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
220 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
221 PC_VCC_ON = 1<<1, /* Switch VCC On */
222 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
223 };
224
225 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
226 enum {
227 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
228 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
229 /* Bit 30: reserved */
230 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
231 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
232 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
233 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
234 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
235 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
236 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
237 /* IRQ from PHY (YUKON only) */
238 IS_TIMINT = 1<<22, /* IRQ from Timer */
239 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
240 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
241 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
242 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
243 /* Receive Queue 1 */
244 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
245 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
246 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
247 /* Receive Queue 2 */
248 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
249 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
250 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
251 /* Synchronous Transmit Queue 1 */
252 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
253 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
254 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
255 /* Asynchronous Transmit Queue 1 */
256 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
257 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
258 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
259 /* Synchronous Transmit Queue 2 */
260 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
261 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
262 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
263 /* Asynchronous Transmit Queue 2 */
264 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
265 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
266 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
267
268 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
269 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
270
271 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
272 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
273 };
274
275
276 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
277 enum {
278 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
279 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
280 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
281 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
282 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
283 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
284 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
285 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
286 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
287 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
288 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
289 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
290 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
291 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
292
293 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
294 | IS_RAM_RD_PAR | IS_RAM_WR_PAR
295 | IS_M1_PAR_ERR | IS_M2_PAR_ERR
296 | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
297 };
298
299 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
300 enum {
301 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
302 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
303 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
304 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
305 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
306 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
307 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
308 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
309 };
310
311 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
312 enum {
313 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
314 /* Bit 3.. 2: reserved */
315 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
316 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
317 };
318
319 /* B2_CHIP_ID 8 bit Chip Identification Number */
320 enum {
321 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
322 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
323 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
324 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
325 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
326 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
327 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
328
329 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
330 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
331 };
332
333 /* B2_TI_CTRL 8 bit Timer control */
334 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
335 enum {
336 TIM_START = 1<<2, /* Start Timer */
337 TIM_STOP = 1<<1, /* Stop Timer */
338 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
339 };
340
341 /* B2_TI_TEST 8 Bit Timer Test */
342 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
343 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
344 enum {
345 TIM_T_ON = 1<<2, /* Test mode on */
346 TIM_T_OFF = 1<<1, /* Test mode off */
347 TIM_T_STEP = 1<<0, /* Test step */
348 };
349
350 /* B2_GP_IO 32 bit General Purpose I/O Register */
351 enum {
352 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
353 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
354 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
355 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
356 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
357 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
358 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
359 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
360 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
361 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
362
363 GP_IO_9 = 1<<9, /* IO_9 pin */
364 GP_IO_8 = 1<<8, /* IO_8 pin */
365 GP_IO_7 = 1<<7, /* IO_7 pin */
366 GP_IO_6 = 1<<6, /* IO_6 pin */
367 GP_IO_5 = 1<<5, /* IO_5 pin */
368 GP_IO_4 = 1<<4, /* IO_4 pin */
369 GP_IO_3 = 1<<3, /* IO_3 pin */
370 GP_IO_2 = 1<<2, /* IO_2 pin */
371 GP_IO_1 = 1<<1, /* IO_1 pin */
372 GP_IO_0 = 1<<0, /* IO_0 pin */
373 };
374
375 /* Descriptor Bit Definition */
376 /* TxCtrl Transmit Buffer Control Field */
377 /* RxCtrl Receive Buffer Control Field */
378 enum {
379 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
380 BMU_STF = 1<<30, /* Start of Frame */
381 BMU_EOF = 1<<29, /* End of Frame */
382 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
383 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
384 /* TxCtrl specific bits */
385 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
386 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
387 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
388 /* RxCtrl specific bits */
389 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
390 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
391 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
392 /* Bit 23..16: BMU Check Opcodes */
393 BMU_CHECK = 0x55<<16, /* Default BMU check */
394 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
395 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
396 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
397 };
398
399 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
400 enum {
401 BSC_START = 1<<1, /* Start Blink Source Counter */
402 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
403 };
404
405 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
406 enum {
407 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
408 };
409
410 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
411 enum {
412 BSC_T_ON = 1<<2, /* Test mode on */
413 BSC_T_OFF = 1<<1, /* Test mode off */
414 BSC_T_STEP = 1<<0, /* Test step */
415 };
416
417 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
418 /* Bit 31..19: reserved */
419 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
420 /* RAM Interface Registers */
421
422 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
423 enum {
424 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
425 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
426
427 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
428 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
429 };
430
431 /* MAC Arbiter Registers */
432 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
433 enum {
434 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
435 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
436 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
437 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
438
439 };
440
441 /* Timeout values */
442 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
443 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
444 #define SK_PKT_TO_MAX 0xffff /* Maximum value */
445 #define SK_RI_TO_53 36 /* RAM interface timeout */
446
447 /* Packet Arbiter Registers */
448 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
449 enum {
450 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
451 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
452 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
453 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
454 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
455 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
456 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
457 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
458 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
459 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
460 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
461 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
462 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
463 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
464 };
465
466 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
467 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
468
469
470 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
471 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
472 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
473 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
474 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
475
476 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
477
478 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
479 enum {
480 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
481 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
482 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
483 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
484 TXA_START_RC = 1<<3, /* Start sync Rate Control */
485 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
486 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
487 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
488 };
489
490 /*
491 * Bank 4 - 5
492 */
493 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
494 enum {
495 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
496 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
497 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
498 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
499 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
500 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
501 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
502 };
503
504
505 enum {
506 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
507 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
508 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
509 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
510 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
511 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
512 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
513 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
514 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
515 };
516
517 /* Queue Register Offsets, use Q_ADDR() to access */
518 enum {
519 B8_Q_REGS = 0x0400, /* base of Queue registers */
520 Q_D = 0x00, /* 8*32 bit Current Descriptor */
521 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
522 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
523 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
524 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
525 Q_BC = 0x30, /* 32 bit Current Byte Counter */
526 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
527 Q_F = 0x38, /* 32 bit Flag Register */
528 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
529 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
530 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
531 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
532 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
533 Q_T2 = 0x40, /* 32 bit Test Register 2 */
534 Q_T3 = 0x44, /* 32 bit Test Register 3 */
535
536 };
537 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
538
539 /* RAM Buffer Register Offsets */
540 enum {
541
542 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
543 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
544 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
545 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
546 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
547 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
548 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
549 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
550 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
551 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
552 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
553 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
554 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
555 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
556 };
557
558 /* Receive and Transmit Queues */
559 enum {
560 Q_R1 = 0x0000, /* Receive Queue 1 */
561 Q_R2 = 0x0080, /* Receive Queue 2 */
562 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
563 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
564 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
565 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
566 };
567
568 /* Different MAC Types */
569 enum {
570 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
571 SK_MAC_GMAC = 1, /* Marvell GMAC */
572 };
573
574 /* Different PHY Types */
575 enum {
576 SK_PHY_XMAC = 0,/* integrated in XMAC II */
577 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
578 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
579 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
580 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
581 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
582 };
583
584 /* PHY addresses (bits 12..8 of PHY address reg) */
585 enum {
586 PHY_ADDR_XMAC = 0<<8,
587 PHY_ADDR_BCOM = 1<<8,
588
589 /* GPHY address (bits 15..11 of SMI control reg) */
590 PHY_ADDR_MARV = 0,
591 };
592
593 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
594
595 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
596 enum {
597 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
598 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
599
600 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
601 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
602 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
603 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
604 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
605 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
606 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
607 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
608 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
609
610 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
611 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
612 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
613 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
614
615 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
616 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
617 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
618 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
619 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
620 };
621
622 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
623 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
624 enum {
625 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
626 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
627 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
628 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
629 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
630 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
631 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
632 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
633 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
634 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
635 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
636 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
637 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
638 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
639 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
640 };
641
642 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
643 enum {
644 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
645
646 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
647 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
648
649 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
650 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
651
652 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
653 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
654 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
655 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
656
657 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
658 };
659
660
661 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
662 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
663 enum {
664 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
665 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
666 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
667 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
668 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
669 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
670 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
671 };
672
673 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
674 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
675 enum {
676 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
677 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
678 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
679
680 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
681 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
682 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
683 };
684
685 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
686 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
687 enum {
688 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
689 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
690 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
691 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
692 };
693
694
695 /* Link LED Counter Registers (GENESIS only) */
696
697 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
698 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
699 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
700 enum {
701 LED_START = 1<<2, /* Start Timer */
702 LED_STOP = 1<<1, /* Stop Timer */
703 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
704 };
705
706 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
707 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
708 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
709 enum {
710 LED_T_ON = 1<<2, /* LED Counter Test mode On */
711 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
712 LED_T_STEP = 1<<0, /* LED Counter Step */
713 };
714
715 /* LNK_LED_REG 8 bit Link LED Register */
716 enum {
717 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
718 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
719 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
720 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
721 LED_ON = 1<<1, /* switch LED on */
722 LED_OFF = 1<<0, /* switch LED off */
723 };
724
725 /* Receive GMAC FIFO (YUKON) */
726 enum {
727 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
728 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
729 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
730 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
731 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
732 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
733 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
734 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
735 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
736 };
737
738
739 /* TXA_TEST 8 bit Tx Arbiter Test Register */
740 enum {
741 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
742 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
743 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
744 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
745 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
746 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
747 };
748
749 /* TXA_STAT 8 bit Tx Arbiter Status Register */
750 enum {
751 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
752 };
753
754
755 /* Q_BC 32 bit Current Byte Counter */
756
757 /* BMU Control Status Registers */
758 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
759 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
760 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
761 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
762 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
763 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
764 /* Q_CSR 32 bit BMU Control/Status Register */
765
766 enum {
767 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
768
769 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
770 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
771 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
772 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
773 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
774 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
775 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
776 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
777 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
778 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
779 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
780 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
781 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
782 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
783 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
784 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
785 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
786 CSR_START = 1<<4, /* Start Rx/Tx Queue */
787 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
788 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
789 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
790 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
791 };
792
793 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
794 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
795 CSR_TRANS_RST)
796 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
797 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
798 CSR_TRANS_RUN)
799
800 /* Q_F 32 bit Flag Register */
801 enum {
802 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
803 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
804 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
805 F_WM_REACHED = 1<<25, /* Watermark reached */
806
807 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
808 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
809 };
810
811 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
812 /* RB_START 32 bit RAM Buffer Start Address */
813 /* RB_END 32 bit RAM Buffer End Address */
814 /* RB_WP 32 bit RAM Buffer Write Pointer */
815 /* RB_RP 32 bit RAM Buffer Read Pointer */
816 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
817 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
818 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
819 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
820 /* RB_PC 32 bit RAM Buffer Packet Counter */
821 /* RB_LEV 32 bit RAM Buffer Level Register */
822
823 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
824 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
825 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
826
827 /* RB_CTRL 8 bit RAM Buffer Control Register */
828 enum {
829 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
830 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
831 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
832 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
833 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
834 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
835 };
836
837 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
838 enum {
839 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
840 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
841 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
842 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
843 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
844 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
845 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
846 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
847
848 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
849 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
850 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
851
852 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
853 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
854 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
855 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
856 };
857
858 /* Counter and Timer constants, for a host clock of 62.5 MHz */
859 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
860 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
861
862 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
863
864 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
865 /* 215 ms at 78.12 MHz */
866
867 #define SK_FACT_62 100 /* is given in percent */
868 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
869 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
870
871
872 /* Transmit GMAC FIFO (YUKON only) */
873 enum {
874 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
875 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
876 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
877
878 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
879 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
880 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
881
882 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
883 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
884 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
885
886 /* Descriptor Poll Timer Registers */
887 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
888 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
889 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
890
891 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
892
893 /* Time Stamp Timer Registers (YUKON only) */
894 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
895 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
896 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
897 };
898
899
900 enum {
901 LINKLED_OFF = 0x01,
902 LINKLED_ON = 0x02,
903 LINKLED_LINKSYNC_OFF = 0x04,
904 LINKLED_LINKSYNC_ON = 0x08,
905 LINKLED_BLINK_OFF = 0x10,
906 LINKLED_BLINK_ON = 0x20,
907 };
908
909 /* GMAC and GPHY Control Registers (YUKON only) */
910 enum {
911 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
912 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
913 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
914 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
915 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
916
917 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
918
919 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
920
921 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
922 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
923 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
924 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
925 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
926
927 /* WOL Pattern Length Registers (YUKON only) */
928
929 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
930 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
931
932 /* WOL Pattern Counter Registers (YUKON only) */
933
934 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
935 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
936 };
937 #define WOL_REGS(port, x) (x + (port)*0x80)
938
939 enum {
940 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
941 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
942 };
943 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
944
945 enum {
946 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
947 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
948 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
949 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
950 };
951
952 /*
953 * Receive Frame Status Encoding
954 */
955 enum {
956 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
957 XMR_FS_LEN_SHIFT = 18,
958 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
959 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
960 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
961 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
962 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
963
964 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
965 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
966 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
967 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
968 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
969 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
970 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
971 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
972 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
973 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
974 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
975 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
976
977 /*
978 * XMR_FS_ERR will be set if
979 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
980 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
981 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
982 * XMR_FS_ERR unless the corresponding bit in the Receive Command
983 * Register is set.
984 */
985 };
986
987 /*
988 ,* XMAC-PHY Registers, indirect addressed over the XMAC
989 */
990 enum {
991 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
992 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
993 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
994 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
995 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
996 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
997 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
998 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
999 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1000
1001 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
1002 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
1003 };
1004 /*
1005 * Broadcom-PHY Registers, indirect addressed over XMAC
1006 */
1007 enum {
1008 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1009 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1010 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1011 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1012 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1013 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1014 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1015 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1016 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1017 /* Broadcom-specific registers */
1018 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1019 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1020 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1021 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1022 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1023 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1024 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1025 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1026
1027 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1028 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1029 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1030 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1031 };
1032
1033 /*
1034 * Marvel-PHY Registers, indirect addressed over GMAC
1035 */
1036 enum {
1037 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1038 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1039 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1040 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1041 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1042 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1043 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1044 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1045 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1046 /* Marvel-specific registers */
1047 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1048 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1049 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1050 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1051 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1052 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1053 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1054 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1055 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1056 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1057 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1058 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1059 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1060 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1061 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1062 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1063 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1064 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1065
1066 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1067 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1068 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1069 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1070 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1071 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1072 };
1073
1074 enum {
1075 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1076 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1077 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1078 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1079 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1080 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1081 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1082 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1083 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1084 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1085 };
1086
1087 enum {
1088 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1089 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1090 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1091 };
1092
1093 enum {
1094 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1095
1096 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1097 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1098 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1099 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1100 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1101 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1102 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1103 };
1104
1105 enum {
1106 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1107 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1108 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1109 };
1110
1111 /* different Broadcom PHY Ids */
1112 enum {
1113 PHY_BCOM_ID1_A1 = 0x6041,
1114 PHY_BCOM_ID1_B2 = 0x6043,
1115 PHY_BCOM_ID1_C0 = 0x6044,
1116 PHY_BCOM_ID1_C5 = 0x6047,
1117 };
1118
1119 /* different Marvell PHY Ids */
1120 enum {
1121 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1122 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1123 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1124 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1125 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1126 };
1127
1128 /* Advertisement register bits */
1129 enum {
1130 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1131 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1132 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1133
1134 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1135 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1136 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1137 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1138 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1139 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1140 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1141 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1142 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1143 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1144 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1145 PHY_AN_100HALF | PHY_AN_100FULL,
1146 };
1147
1148 /* Xmac Specific */
1149 enum {
1150 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1151 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1152 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1153
1154 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1155 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1156 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1157 };
1158
1159 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1160 enum {
1161 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1162 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1163 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1164 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1165 };
1166
1167
1168 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1169 enum {
1170 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1171 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1172 };
1173
1174 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1175 enum {
1176 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1177 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1178 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1179 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1180 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1181 };
1182
1183 /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
1184 enum {
1185 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1186 X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
1187 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1188 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1189 };
1190
1191 /* Broadcom-Specific */
1192 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1193 enum {
1194 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1195 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1196 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1197 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1198 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1199 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1200 };
1201
1202 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1203 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1204 enum {
1205 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1206 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1207 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1208 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1209 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1210 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1211 /* Bit 9..8: reserved */
1212 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1213 };
1214
1215 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1216 enum {
1217 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1218 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1219 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1220 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1221 };
1222
1223 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1224 enum {
1225 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1226 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1227 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1228 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1229 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1230 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1231 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1232 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1233 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1234 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1235 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1236 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1237 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1238 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1239 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1240 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1241 };
1242
1243 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1244 enum {
1245 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1246 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1247 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1248 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1249 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1250 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1251 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1252 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1253 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1254 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1255 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1256 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1257 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1258 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1259 };
1260
1261 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1262 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1263 enum {
1264 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1265
1266 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1267 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1268 };
1269
1270
1271 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1272 enum {
1273 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1274
1275 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1276 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1277 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1278
1279 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1280 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1281 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1282 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1283 /* Bit 11: reserved */
1284 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1285 /* Bit 9.. 8: reserved */
1286 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1287 /* Bit 6: reserved */
1288 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1289 /* Bit 4: reserved */
1290 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1291 };
1292
1293 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1294 enum {
1295 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1296 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1297 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1298 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1299 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1300 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1301 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1302 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1303 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1304 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1305 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1306 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1307 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1308 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1309 };
1310 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1311
1312 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1313 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1314 enum {
1315 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1316 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1317 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1318 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1319 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1320 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1321 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1322 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1323 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1324 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1325 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1326 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1327 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1328 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1329 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1330 };
1331 #define PHY_B_DEF_MSK \
1332 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1333 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1334
1335 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1336 enum {
1337 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1338 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1339 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1340 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1341 };
1342 /*
1343 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1344 */
1345 enum {
1346 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1347 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1348 };
1349
1350 /** Marvell-Specific */
1351 enum {
1352 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1353 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1354 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1355
1356 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1357 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1358 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1359 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1360 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1361 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1362 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1363 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1364 };
1365
1366 /* special defines for FIBER (88E1011S only) */
1367 enum {
1368 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1369 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1370 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1371 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1372 };
1373
1374 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1375 enum {
1376 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1377 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1378 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1379 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1380 };
1381
1382 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1383 enum {
1384 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1385 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1386 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1387 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1388 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1389 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1390 };
1391
1392 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1393 enum {
1394 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1395 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1396 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1397 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1398 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1399 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1400 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1401 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1402 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1403 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1404 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1405 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1406 };
1407
1408 enum {
1409 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1410 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1411 };
1412
1413 enum {
1414 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1415 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1416 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1417 };
1418
1419 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1420 enum {
1421 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1422 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1423 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1424 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1425 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1426
1427 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1428 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1429
1430 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1431 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1432 };
1433
1434 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1435 enum {
1436 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1437 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1438 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1439 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1440 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1441 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1442 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1443 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1444 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1445 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1446 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1447 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1448 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1449 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1450 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1451 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1452 };
1453
1454 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1455
1456 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1457 enum {
1458 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1459 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1460 };
1461
1462 enum {
1463 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1464 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1465 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1466 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1467 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1468 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1469 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1470 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1471 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1472 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1473 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1474 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1475
1476 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1477 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1478 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1479
1480 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1481 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1482
1483 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1484 };
1485
1486 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1487 enum {
1488 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1489 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1490
1491 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1492 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1493 /* (88E1011 only) */
1494 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
1495 /* (88E1011 only) */
1496 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1497 /* (88E1111 only) */
1498 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1499 /* !!! Errata in spec. (1 = disable) */
1500 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1501 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1502 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1503 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1504 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1505 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1506
1507 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1508 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1509 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1510
1511 #define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1512 /* 100=5x; 101=6x; 110=7x; 111=8x */
1513 enum {
1514 MAC_TX_CLK_0_MHZ = 2,
1515 MAC_TX_CLK_2_5_MHZ = 6,
1516 MAC_TX_CLK_25_MHZ = 7,
1517 };
1518
1519 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1520 enum {
1521 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1522 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1523 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1524 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1525 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1526 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1527 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1528 /* (88E1111 only) */
1529 };
1530 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1531 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1532
1533 enum {
1534 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
1535 /* (88E1011 only) */
1536 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1537 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1538 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1539 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1540 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1541 };
1542
1543 enum {
1544 PULS_NO_STR = 0, /* no pulse stretching */
1545 PULS_21MS = 1, /* 21 ms to 42 ms */
1546 PULS_42MS = 2, /* 42 ms to 84 ms */
1547 PULS_84MS = 3, /* 84 ms to 170 ms */
1548 PULS_170MS = 4, /* 170 ms to 340 ms */
1549 PULS_340MS = 5, /* 340 ms to 670 ms */
1550 PULS_670MS = 6, /* 670 ms to 1.3 s */
1551 PULS_1300MS = 7, /* 1.3 s to 2.7 s */
1552 };
1553
1554
1555 enum {
1556 BLINK_42MS = 0, /* 42 ms */
1557 BLINK_84MS = 1, /* 84 ms */
1558 BLINK_170MS = 2, /* 170 ms */
1559 BLINK_340MS = 3, /* 340 ms */
1560 BLINK_670MS = 4, /* 670 ms */
1561 };
1562
1563 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1564 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1565 /* Bit 13..12: reserved */
1566 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1567 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1568 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1569 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1570 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1571 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1572
1573 enum {
1574 MO_LED_NORM = 0,
1575 MO_LED_BLINK = 1,
1576 MO_LED_OFF = 2,
1577 MO_LED_ON = 3,
1578 };
1579
1580 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1581 enum {
1582 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1583 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1584 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1585 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1586 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
1587 };
1588
1589 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1590 enum {
1591 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1592 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1593 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1594 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1595 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1596 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1597 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1598 /* (88E1111 only) */
1599 /* Bit 9.. 4: reserved (88E1011 only) */
1600 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1601 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1602 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1603 };
1604
1605 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1606 enum {
1607 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1608 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1609 /* (88E1111 only) */
1610 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1611 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1612 /* (88E1111 only) */
1613 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1614 };
1615
1616 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1617 enum {
1618 CABD_STAT_NORMAL= 0,
1619 CABD_STAT_SHORT = 1,
1620 CABD_STAT_OPEN = 2,
1621 CABD_STAT_FAIL = 3,
1622 };
1623
1624 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1625 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1626 /* Bit 15..12: reserved (used internally) */
1627 enum {
1628 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1629 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1630 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1631 };
1632
1633 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1634 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1635 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1636
1637 enum {
1638 LED_PAR_CTRL_COLX = 0x00,
1639 LED_PAR_CTRL_ERROR = 0x01,
1640 LED_PAR_CTRL_DUPLEX = 0x02,
1641 LED_PAR_CTRL_DP_COL = 0x03,
1642 LED_PAR_CTRL_SPEED = 0x04,
1643 LED_PAR_CTRL_LINK = 0x05,
1644 LED_PAR_CTRL_TX = 0x06,
1645 LED_PAR_CTRL_RX = 0x07,
1646 LED_PAR_CTRL_ACT = 0x08,
1647 LED_PAR_CTRL_LNK_RX = 0x09,
1648 LED_PAR_CTRL_LNK_AC = 0x0a,
1649 LED_PAR_CTRL_ACT_BL = 0x0b,
1650 LED_PAR_CTRL_TX_BL = 0x0c,
1651 LED_PAR_CTRL_RX_BL = 0x0d,
1652 LED_PAR_CTRL_COL_BL = 0x0e,
1653 LED_PAR_CTRL_INACT = 0x0f
1654 };
1655
1656 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1657 enum {
1658 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1659 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1660 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1661 };
1662
1663
1664 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1665 enum {
1666 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1667 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1668 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1669 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1670 };
1671
1672 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1673 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1674 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1675 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1676
1677 /* GMAC registers */
1678 /* Port Registers */
1679 enum {
1680 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1681 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1682 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1683 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1684 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1685 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1686 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1687 /* Source Address Registers */
1688 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1689 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1690 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1691 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1692 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1693 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1694
1695 /* Multicast Address Hash Registers */
1696 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1697 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1698 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1699 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1700
1701 /* Interrupt Source Registers */
1702 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1703 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1704 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1705
1706 /* Interrupt Mask Registers */
1707 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1708 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1709 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1710
1711 /* Serial Management Interface (SMI) Registers */
1712 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1713 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1714 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1715 };
1716
1717 /* MIB Counters */
1718 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1719 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1720
1721 /*
1722 * MIB Counters base address definitions (low word) -
1723 * use offset 4 for access to high word (32 bit r/o)
1724 */
1725 enum {
1726 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1727 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1728 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1729 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1730 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1731 /* GM_MIB_CNT_BASE + 40: reserved */
1732 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1733 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1734 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1735 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1736 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1737 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1738 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1739 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1740 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1741 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1742 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1743 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1744 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1745 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1746 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1747 /* GM_MIB_CNT_BASE + 168: reserved */
1748 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1749 /* GM_MIB_CNT_BASE + 184: reserved */
1750 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1751 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1752 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1753 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1754 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1755 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1756 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1757 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1758 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1759 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1760 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1761 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1762 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1763
1764 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1765 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1766 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1767 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1768 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1769 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1770 };
1771
1772 /* GMAC Bit Definitions */
1773 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1774 enum {
1775 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1776 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1777 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1778 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1779 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1780 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1781 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1782 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1783
1784 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1785 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1786 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1787 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1788 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1789 };
1790
1791 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1792 enum {
1793 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1794 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1795 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1796 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1797 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1798 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1799 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1800 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1801 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1802 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1803 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1804 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1805 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1806 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1807 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1808 };
1809
1810 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1811 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1812
1813 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1814 enum {
1815 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1816 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1817 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1818 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1819 };
1820
1821 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1822 #define TX_COL_DEF 0x04 /* late collision after 64 byte */
1823
1824 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1825 enum {
1826 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1827 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1828 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1829 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1830 };
1831
1832 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1833 enum {
1834 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1835 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1836 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1837
1838 TX_JAM_LEN_DEF = 0x03,
1839 TX_JAM_IPG_DEF = 0x0b,
1840 TX_IPG_JAM_DEF = 0x1c,
1841 };
1842
1843 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1844 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1845 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1846
1847
1848 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1849 enum {
1850 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1851 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1852 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1853 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1854 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1855 };
1856
1857 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1858 #define DATA_BLIND_DEF 0x04
1859
1860 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1861 #define IPG_DATA_DEF 0x1e
1862
1863 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1864 enum {
1865 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1866 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1867 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1868 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1869 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1870 };
1871
1872 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1873 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1874
1875 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1876 enum {
1877 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1878 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1879 };
1880
1881 /* Receive Frame Status Encoding */
1882 enum {
1883 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1884 GMR_FS_LEN_SHIFT = 16,
1885 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1886 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1887 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1888 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1889 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1890 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1891 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1892 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1893 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1894 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1895 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1896
1897 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1898 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1899
1900 /*
1901 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1902 */
1903 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1904 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1905 GMR_FS_JABBER,
1906 /* Rx GMAC FIFO Flush Mask (default) */
1907 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1908 GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
1909 };
1910
1911 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1912 enum {
1913 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1914 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1915 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1916
1917 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1918 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1919 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1920 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1921 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1922 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1923 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1924 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1925 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1926 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1927 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1928
1929 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1930 };
1931
1932
1933 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1934 enum {
1935 GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
1936 GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
1937 GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
1938
1939 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1940 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1941 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1942 };
1943
1944 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1945 enum {
1946 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1947 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1948 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1949 };
1950
1951 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1952 enum {
1953 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1954 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1955 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1956 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1957 GMC_PAUSE_ON = 1<<3, /* Pause On */
1958 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1959 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1960 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1961 };
1962
1963 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1964 enum {
1965 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1966 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1967 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1968 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1969 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1970 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1971 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1972 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1973 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1974 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1975 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1976 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1977 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1978 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1979 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1980 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1981 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1982 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1983 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1984 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1985 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1986 /* Bits 7..2: reserved */
1987 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1988 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1989 };
1990
1991 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1992 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1993 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1994
1995 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1996 #define GPC_FRC10MBIT_HALF 0
1997 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
1998 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
1999 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
2000
2001 /* auto-negotiation with limited advertised speeds */
2002 /* mix only with master/slave settings (for copper) */
2003 #define GPC_ADV_1000_HALF GPC_ANEG_2
2004 #define GPC_ADV_1000_FULL GPC_ANEG_3
2005 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
2006
2007 /* master/slave settings */
2008 /* only for copper with 1000 Mbps */
2009 #define GPC_FORCE_MASTER 0
2010 #define GPC_FORCE_SLAVE GPC_ANEG_0
2011 #define GPC_PREF_MASTER GPC_ANEG_1
2012 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
2013
2014 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2015 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2016 enum {
2017 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
2018 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
2019 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
2020 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
2021 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
2022 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
2023
2024 #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
2025
2026 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2027 /* Bits 15.. 2: reserved */
2028 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2029 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2030
2031
2032 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2033 WOL_CTL_LINK_CHG_OCC = 1<<15,
2034 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
2035 WOL_CTL_PATTERN_OCC = 1<<13,
2036 WOL_CTL_CLEAR_RESULT = 1<<12,
2037 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2038 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
2039 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
2040 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
2041 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
2042 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
2043 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2044 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
2045 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
2046 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
2047 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
2048 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
2049 };
2050
2051 #define WOL_CTL_DEFAULT \
2052 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
2053 WOL_CTL_DIS_PME_ON_PATTERN | \
2054 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
2055 WOL_CTL_DIS_LINK_CHG_UNIT | \
2056 WOL_CTL_DIS_PATTERN_UNIT | \
2057 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2058
2059 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2060 #define WOL_CTL_PATT_ENA(x) (1 << (x))
2061
2062
2063 /* XMAC II registers */
2064 enum {
2065 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2066 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2067 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2068 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2069 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2070 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2071 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2072 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2073 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2074 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2075 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2076 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2077 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2078 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2079 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2080 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2081 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2082 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2083 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2084 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2085 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2086 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2087 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2088 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2089 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2090
2091 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2092 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2093 };
2094
2095 enum {
2096 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2097 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2098 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2099 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2100 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2101 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2102 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2103 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2104 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2105 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2106 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2107 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2108 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2109 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2110 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2111 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2112 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2113 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2114 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2115 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2116 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2117 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2118 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2119 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2120 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2121 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2122 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2123 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2124 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2125 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2126 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2127 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2128 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2129 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2130 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2131 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2132 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2133 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2134 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2135 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2136 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2137 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2138 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2139 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2140 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2141 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2142 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2143 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2144 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2145 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2146 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2147 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2148 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2149 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2150 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2151 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2152 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2153 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2154 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2155 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2156 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2157 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2158 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2159 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2160 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2161 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2162 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2163 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2164 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2165 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2166 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2167 };
2168
2169 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2170 enum {
2171 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2172 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2173 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2174 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2175 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2176 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2177 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2178 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2179 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2180 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2181 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2182 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2183 };
2184
2185
2186 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2187 enum {
2188 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2189 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2190 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2191 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2192 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2193 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2194 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2195 };
2196
2197 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2198 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2199
2200
2201 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2202 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2203
2204
2205 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2206 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2207
2208
2209 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2210 enum {
2211 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2212 /* inrange error packets */
2213 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2214 /* jumbo packets */
2215 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2216 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2217 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2218 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2219 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2220 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2221 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2222 };
2223
2224
2225 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2226 enum {
2227 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2228 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2229 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2230 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2231 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2232 };
2233
2234
2235 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2236 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2237 enum {
2238 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2239 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2240 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2241 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2242 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2243 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2244 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2245 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2246 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2247 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2248 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2249 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2250 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2251 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2252 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2253
2254 XM_IMSK_DISABLE = 0xffff,
2255 };
2256
2257 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2258 enum {
2259 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2260 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2261 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2262 };
2263
2264
2265 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2266 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2267 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2268
2269 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2270 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2271 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2272 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2273
2274
2275 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2276 enum {
2277 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2278 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2279 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2280 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2281 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2282 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2283 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2284 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2285 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2286 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2287 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
2288 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2289 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2290 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2291 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2292 };
2293
2294 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2295 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2296 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2297
2298
2299 /* XM_DEV_ID 32 bit r/o Device ID Register */
2300 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2301 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2302
2303
2304 /* XM_MODE 32 bit r/w Mode Register */
2305 enum {
2306 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2307 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2308 /* extern generated */
2309 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2310 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2311 /* intern generated */
2312 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2313 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2314 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2315 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2316 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2317 /* intern generated */
2318 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2319 /* intern generated */
2320 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2321 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2322 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2323 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2324 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2325 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2326 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2327 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2328 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2329 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2330 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2331 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2332 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2333 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2334 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2335 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2336 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2337 };
2338
2339 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2340 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2341 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2342
2343 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2344 enum {
2345 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2346 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2347 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2348 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2349 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2350 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2351 };
2352
2353
2354 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2355 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2356 enum {
2357 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2358 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2359 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2360 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2361 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2362 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2363 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2364 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2365 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2366 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2367 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2368 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2369 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2370 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2371 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2372 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2373 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2374 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2375 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2376 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2377 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2378 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2379 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2380 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2381 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2382 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2383 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2384 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2385 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2386 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2387 };
2388
2389 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2390
2391 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2392 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2393 enum {
2394 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2395 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2396 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2397 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2398 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2399 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2400 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2401 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2402 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2403 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2404 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2405 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2406 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2407 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2408 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2409 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2410 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2411 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2412 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2413 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2414 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2415 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2416 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2417 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2418 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2419 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2420 };
2421
2422
2423 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2424
2425 struct skge_rx_desc {
2426 u32 control;
2427 u32 next_offset;
2428 u32 dma_lo;
2429 u32 dma_hi;
2430 u32 status;
2431 u32 timestamp;
2432 u16 csum2;
2433 u16 csum1;
2434 u16 csum2_start;
2435 u16 csum1_start;
2436 };
2437
2438 struct skge_tx_desc {
2439 u32 control;
2440 u32 next_offset;
2441 u32 dma_lo;
2442 u32 dma_hi;
2443 u32 status;
2444 u32 csum_offs;
2445 u16 csum_write;
2446 u16 csum_start;
2447 u32 rsvd;
2448 };
2449
2450 struct skge_element {
2451 struct skge_element *next;
2452 void *desc;
2453 struct io_buffer *iob;
2454 };
2455
2456 struct skge_ring {
2457 struct skge_element *to_clean;
2458 struct skge_element *to_use;
2459 struct skge_element *start;
2460 };
2461
2462
2463 struct skge_hw {
2464 u32 regs;
2465 struct pci_device *pdev;
2466 u32 intr_mask;
2467 struct net_device *dev[2];
2468
2469 u8 chip_id;
2470 u8 chip_rev;
2471 u8 copper;
2472 u8 ports;
2473 u8 phy_type;
2474
2475 u32 ram_size;
2476 u32 ram_offset;
2477 u16 phy_addr;
2478 };
2479
2480 enum pause_control {
2481 FLOW_MODE_NONE = 1, /* No Flow-Control */
2482 FLOW_MODE_LOC_SEND = 2, /* Local station sends PAUSE */
2483 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2484 FLOW_MODE_SYM_OR_REM = 4, /* Both stations may send PAUSE or
2485 * just the remote station may send PAUSE
2486 */
2487 };
2488
2489 enum pause_status {
2490 FLOW_STAT_INDETERMINATED=0, /* indeterminated */
2491 FLOW_STAT_NONE, /* No Flow Control */
2492 FLOW_STAT_REM_SEND, /* Remote Station sends PAUSE */
2493 FLOW_STAT_LOC_SEND, /* Local station sends PAUSE */
2494 FLOW_STAT_SYMMETRIC, /* Both station may send PAUSE */
2495 };
2496
2497
2498 struct skge_port {
2499 struct skge_hw *hw;
2500 struct net_device *netdev;
2501 int port;
2502
2503 struct skge_ring tx_ring;
2504 struct skge_ring rx_ring;
2505
2506 enum pause_control flow_control;
2507 enum pause_status flow_status;
2508 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2509 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2510 u16 speed; /* SPEED_1000, SPEED_100, ... */
2511 u32 advertising;
2512
2513 void *mem; /* PCI memory for rings */
2514 u32 dma;
2515 int use_xm_link_timer;
2516 };
2517
2518
2519 /* Register accessor for memory mapped device */
skge_read32(const struct skge_hw * hw,int reg)2520 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2521 {
2522 return readl(hw->regs + reg);
2523 }
2524
skge_read16(const struct skge_hw * hw,int reg)2525 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2526 {
2527 return readw(hw->regs + reg);
2528 }
2529
skge_read8(const struct skge_hw * hw,int reg)2530 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2531 {
2532 return readb(hw->regs + reg);
2533 }
2534
skge_write32(const struct skge_hw * hw,int reg,u32 val)2535 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2536 {
2537 writel(val, hw->regs + reg);
2538 }
2539
skge_write16(const struct skge_hw * hw,int reg,u16 val)2540 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2541 {
2542 writew(val, hw->regs + reg);
2543 }
2544
skge_write8(const struct skge_hw * hw,int reg,u8 val)2545 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2546 {
2547 writeb(val, hw->regs + reg);
2548 }
2549
2550 /* MAC Related Registers inside the device. */
2551 #define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2552 #define SK_XMAC_REG(port, reg) \
2553 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2554
xm_read32(const struct skge_hw * hw,int port,int reg)2555 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2556 {
2557 u32 v;
2558 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2559 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2560 return v;
2561 }
2562
xm_read16(const struct skge_hw * hw,int port,int reg)2563 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2564 {
2565 return skge_read16(hw, SK_XMAC_REG(port,reg));
2566 }
2567
xm_write32(const struct skge_hw * hw,int port,int r,u32 v)2568 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2569 {
2570 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2571 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2572 }
2573
xm_write16(const struct skge_hw * hw,int port,int r,u16 v)2574 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2575 {
2576 skge_write16(hw, SK_XMAC_REG(port,r), v);
2577 }
2578
xm_outhash(const struct skge_hw * hw,int port,int reg,const u8 * hash)2579 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2580 const u8 *hash)
2581 {
2582 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2583 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2584 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2585 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2586 }
2587
xm_outaddr(const struct skge_hw * hw,int port,int reg,const u8 * addr)2588 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2589 const u8 *addr)
2590 {
2591 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2592 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2593 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2594 }
2595
2596 #define SK_GMAC_REG(port,reg) \
2597 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2598
gma_read16(const struct skge_hw * hw,int port,int reg)2599 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2600 {
2601 return skge_read16(hw, SK_GMAC_REG(port,reg));
2602 }
2603
gma_read32(const struct skge_hw * hw,int port,int reg)2604 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2605 {
2606 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2607 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2608 }
2609
gma_write16(const struct skge_hw * hw,int port,int r,u16 v)2610 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2611 {
2612 skge_write16(hw, SK_GMAC_REG(port,r), v);
2613 }
2614
gma_set_addr(struct skge_hw * hw,int port,int reg,const u8 * addr)2615 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2616 const u8 *addr)
2617 {
2618 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2619 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2620 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2621 }
2622
2623 #endif
2624