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Searched refs:XOR (Results 1 – 25 of 263) sorted by relevance

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/external/openssh/openbsd-compat/
Dchacha_private.h41 #define XOR(v,w) ((v) ^ (w)) macro
46 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
47 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
48 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
171 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/external/openssh/
Dchacha.c42 #define XOR(v,w) ((v) ^ (w)) macro
47 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
48 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
49 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
50 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
171 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dblend_jit.cpp322 result[0] = XOR(OR(src[0], dst[0]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
323 result[1] = XOR(OR(src[1], dst[1]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
324 result[2] = XOR(OR(src[2], dst[2]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
325 result[3] = XOR(OR(src[3], dst[3]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
331 result[0] = AND(XOR(src[0], VIMMED1(0xFFFFFFFF)), dst[0]); in LogicOpFunc()
332 result[1] = AND(XOR(src[1], VIMMED1(0xFFFFFFFF)), dst[1]); in LogicOpFunc()
333 result[2] = AND(XOR(src[2], VIMMED1(0xFFFFFFFF)), dst[2]); in LogicOpFunc()
334 result[3] = AND(XOR(src[3], VIMMED1(0xFFFFFFFF)), dst[3]); in LogicOpFunc()
339 result[0] = XOR(src[0], VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
340 result[1] = XOR(src[1], VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-xor-01.ll1 ; Test vector XOR.
5 ; Test a v16i8 XOR.
14 ; Test a v8i16 XOR.
23 ; Test a v4i32 XOR.
32 ; Test a v2i64 XOR.
Datomicrmw-xor-01.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xff000000.
91 ; Check XORs of 1. We XOR the rotated word with 0x01000000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7f000000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
Datomicrmw-xor-02.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xffff0000.
91 ; Check XORs of 1. We XOR the rotated word with 0x00010000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7fff0000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
Dvec-or-02.ll20 ; ...and again with the XOR applied to the other operand of the AND.
48 ; ...and again with the XOR applied to the other operand of the AND.
73 ; ...and again with the XOR applied to the other operand of the AND.
97 ; ...and again with the XOR applied to the other operand of the AND.
Datomicrmw-xor-06.ll5 ; Check XOR of a variable.
14 ; Check XOR of 1, which needs a temporary.
Drxsbg-01.ll65 ; Test a case with just a rotate (using XOR for the rotate combination too,
114 ; Check the handling of zext and XOR, which can use ROSBG.
/external/llvm/lib/Target/Lanai/
DLanaiAluCode.h30 XOR = 0x06, enumerator
91 case XOR: in lanaiAluCodeToString()
112 .Case("xor", XOR) in stringToLanaiAluCode()
133 case ISD::XOR: in isdToLanaiAluCode()
134 return AluCode::XOR; in isdToLanaiAluCode()
/external/llvm/test/Transforms/InstCombine/
Dzext.ll39 ; CHECK-NEXT: [[XOR:%.*]] = and <2 x i64> [[TMP1]], <i64 23, i64 42>
40 ; CHECK-NEXT: ret <2 x i64> [[XOR]]
54 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[ZEXT1]], 1
55 ; CHECK-NEXT: [[ZEXT2:%.*]] = zext i32 [[XOR]] to i64
67 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i64> [[ZEXT1]], <i64 1, i64 1>
68 ; CHECK-NEXT: ret <2 x i64> [[XOR]]
/external/iptables/extensions/
Dlibxt_CONNMARK.man5 Zero out the bits given by \fImask\fP and XOR \fIvalue\fP into the ctmark.
14 nfmark to XOR into the ctmark. \fIctmask\fP and \fInfmask\fP default to
24 ctmark to XOR into the nfmark. \fIctmask\fP and \fInfmask\fP default to
40 Binary XOR the ctmark with \fIbits\fP. (Mnemonic for \fB\-\-set\-xmark\fP
/external/llvm/lib/Target/Mips/
DMipsCondMov.td201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
234 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
235 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
246 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
248 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
255 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
259 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
/external/selinux/checkpolicy/
Dpolicy_scan.l171 XOR { return(XOR); }
272 "^" { return (XOR); }
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_32.c177 FAIL_IF(push_inst(compiler, XOR | S(src1) | T(src2) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
193 …FAIL_IF(push_inst(compiler, XOR | S(TMP_REG1) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FL… in emit_single_op()
194 FAIL_IF(push_inst(compiler, XOR | S(dst) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
250 FAIL_IF(push_inst(compiler, XOR | S(src1) | T(src2) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
269 …FAIL_IF(push_inst(compiler, XOR | S(TMP_REG1) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FL… in emit_single_op()
270 FAIL_IF(push_inst(compiler, XOR | S(dst) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
324 EMIT_LOGICAL(XORI, XOR); in emit_single_op()
DsljitNativeMIPS_64.c269 FAIL_IF(push_inst(compiler, XOR | S(src1) | T(src2) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
285 …FAIL_IF(push_inst(compiler, XOR | S(TMP_REG1) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FL… in emit_single_op()
286 FAIL_IF(push_inst(compiler, XOR | S(dst) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
342 FAIL_IF(push_inst(compiler, XOR | S(src1) | T(src2) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
361 …FAIL_IF(push_inst(compiler, XOR | S(TMP_REG1) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FL… in emit_single_op()
362 FAIL_IF(push_inst(compiler, XOR | S(dst) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG)); in emit_single_op()
419 EMIT_LOGICAL(XORI, XOR); in emit_single_op()
/external/valgrind/none/tests/mips64/
Dlogical_instructions.c7 OR, ORI, XOR, XORI enumerator
80 case XOR: in main()
/external/llvm/test/CodeGen/X86/
Dwiden_bitops-1.ll6 ; AND/XOR/OR i32 as v4i8
67 ; AND/XOR/OR i32 as v8i4
128 ; AND/XOR/OR v4i8 as i32
183 ; AND/XOR/OR v8i4 as i32
/external/pdfium/xfa/fxbarcode/qrcode/
DBC_QRCoderBitVector.h29 void XOR(CBC_QRCoderBitVector* other, int32_t& e);
/external/proguard/src/proguard/evaluation/value/
DCompositeIntegerValue.java41 public static final byte XOR = '^'; field in CompositeIntegerValue
DCompositeLongValue.java41 public static final byte XOR = '^'; field in CompositeLongValue
/external/llvm/test/CodeGen/AMDGPU/
Dxor.ll45 ; SI: s_xor_b64 [[XOR:vcc]], [[CMP0]], [[CMP1]]
63 ; SI: v_xor_b32_e32 [[XOR:v[0-9]+]], [[A]], [[B]]
64 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[XOR]]
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/util/
DSyntheticAccessorFSM.java202 public static final int XOR = SyntheticAccessorResolver.XOR_ASSIGNMENT; field in SyntheticAccessorFSM
424 mathOp = XOR; in test()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp153 case ISD::XOR: in LegalizeOp()
278 !TLI.isOperationLegalOrCustom(ISD::XOR, VT) || in ExpandVSELECT()
292 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); in ExpandVSELECT()
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dbit-tracking.ll6 ; Reduce down to a single XOR

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