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Searched refs:ZEXTLOAD (Results 1 – 25 of 54) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h694 ZEXTLOAD, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h830 ZEXTLOAD, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in SystemZTargetLowering()
68 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); in SystemZTargetLowering()
72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); in SystemZTargetLowering()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp689 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
913 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
2381 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { in visitAND()
2382 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, in visitAND()
2403 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { in visitAND()
2404 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, in visitAND()
2434 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { in visitAND()
2438 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, in visitAND()
2452 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { in visitAND()
2474 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, in visitAND()
[all …]
DLegalizeDAG.cpp594 HiExtType = ISD::ZEXTLOAD; in ExpandUnalignedLoad()
599 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in ExpandUnalignedLoad()
614 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in ExpandUnalignedLoad()
1214 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeOp()
1227 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeOp()
1252 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), in LegalizeOp()
1290 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, in LegalizeOp()
1363 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; in LegalizeOp()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp103 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
116 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
117 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
118 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
135 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
DR600ISelLowering.cpp57 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
58 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
59 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
1592 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
DAMDGPUInstructions.td252 return L->getExtensionType() == ISD::ZEXTLOAD ||
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXISelLowering.cpp56 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); in PTXTargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
482 IntExt = ISD::ZEXTLOAD; in tryLoadOfLoadIntrinsic()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp961 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
1186 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
3021 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
3038 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
3041 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
3183 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
3197 case ISD::ZEXTLOAD: in visitAND()
3206 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
3249 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
3277 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
[all …]
DSelectionDAGDumper.cpp504 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
DLegalizeDAG.cpp705 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
720 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
746 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), in LegalizeLoadOps()
787 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, in LegalizeLoadOps()
870 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT, in LegalizeLoadOps()
DTargetLowering.cpp1448 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { in SimplifySetCC()
3357 HiExtType = ISD::ZEXTLOAD; in expandUnalignedLoad()
3362 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in expandUnalignedLoad()
3380 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in expandUnalignedLoad()
DLegalizeVectorOps.cpp607 case ISD::ZEXTLOAD: in ExpandLoad()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp129 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in XCoreTargetLowering()
133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); in XCoreTargetLowering()
451 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in AlphaTargetLowering()
65 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand); in AlphaTargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp57 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in BlackfinTargetLowering()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp133 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp128 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); in XCoreTargetLowering()
461 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp118 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in SPUTargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom); in SPUTargetLowering()
728 } else if (ExtType == ISD::ZEXTLOAD) { in LowerLOAD()
2793 case ISD::ZEXTLOAD: in LowerOperation()
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
DCodeGenPrepare.cpp969 LType = ISD::ZEXTLOAD; in MoveExtToFormExtLoad()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MipsTargetLowering()
1871 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, in WriteByValArg()
1892 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, in WriteByValArg()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MBlazeTargetLowering()

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