Searched refs:ZIP2 (Results 1 – 11 of 11) sorted by relevance
| /external/libhevc/decoder/arm64/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 245 ZIP2 v15.8b, v14.8b, v15.8b
248 ZIP2 v17.8b, v16.8b, v17.8b
252 ZIP2 v21.8b, v20.8b, v21.8b
255 ZIP2 v23.8b, v22.8b, v23.8b
264 ZIP2 v26.8h, v14.8h, v16.8h
267 ZIP2 v19.8h, v20.8h, v22.8h
270 ZIP2 v20.4s, v27.4s, v25.4s
273 ZIP2 v22.4s, v26.4s, v19.4s
311 ZIP2 v15.8b, v14.8b, v15.8b
314 ZIP2 v17.8b, v16.8b, v17.8b
[all …]
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| /external/libhevc/common/arm64/ |
| D | ihevc_sao_edge_offset_class1_chroma.s | 212 ZIP2 v17.8b, v5.8b, v17.8b
237 ZIP2 v25.8b, v24.8b, v25.8b
290 ZIP2 v25.8b, v24.8b, v25.8b
378 ZIP2 v17.8b, v5.8b, v17.8b
400 ZIP2 v25.8b, v24.8b, v25.8b
440 ZIP2 v25.8b, v24.8b, v25.8b
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| D | ihevc_sao_band_offset_chroma.s | 387 ZIP2 v6.8b, v5.8b, v6.8b
395 ZIP2 v14.8b, v13.8b, v14.8b
406 ZIP2 v18.8b, v17.8b, v18.8b
412 ZIP2 v22.8b, v21.8b, v22.8b
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| D | ihevc_sao_edge_offset_class0_chroma.s | 247 ZIP2 v17.8b, v16.8b, v17.8b
276 ZIP2 v27.8b, v26.8b, v27.8b //II
429 ZIP2 v17.8b, v16.8b, v17.8b
456 ZIP2 v27.8b, v26.8b, v27.8b //II
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| D | ihevc_sao_edge_offset_class3_chroma.s | 464 ZIP2 v23.8b, v22.8b, v23.8b //I
599 ZIP2 v25.8b, v24.8b, v25.8b //II
629 ZIP2 v23.8b, v22.8b, v23.8b //III
727 ZIP2 v23.8b, v22.8b, v23.8b
914 ZIP2 v25.8b, v24.8b, v25.8b
1101 ZIP2 v25.8b, v24.8b, v25.8b
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| D | ihevc_sao_edge_offset_class2_chroma.s | 481 ZIP2 v23.8b, v22.8b, v23.8b //I
609 ZIP2 v25.8b, v24.8b, v25.8b //II
646 ZIP2 v23.8b, v22.8b, v23.8b //III
737 ZIP2 v25.8b, v24.8b, v25.8b
903 ZIP2 v25.8b, v24.8b, v25.8b
1066 ZIP2 v25.8b, v24.8b, v25.8b
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 102 ZIP2, enumerator
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| D | AArch64SchedKryoDetails.td | 2310 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2346 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
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| D | AArch64ISelLowering.cpp | 878 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2"; in getTargetNodeName()
5492 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
5651 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
5664 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 203 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
3731 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4650 ### ZIP2 ### subsection
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