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/external/v8/tools/clang/blink_gc_plugin/tests/
Ddestructor_access_finalized_field.txt1 destructor_access_finalized_field.cpp:18:9: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
7 destructor_access_finalized_field.cpp:19:5: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
13 destructor_access_finalized_field.cpp:20:5: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
Ddestructor_eagerly_finalized.txt1 …cpp:26:5: warning: [blink-gc] Finalizer '~HeapObjectEagerFinalizedAlso' accesses eagerly finalized…
7 …cpp:27:5: warning: [blink-gc] Finalizer '~HeapObjectEagerFinalizedAlso' accesses eagerly finalized…
/external/v8/tools/clang/blink_gc_plugin/tests/legacy_naming/
Ddestructor_access_finalized_field.txt1 destructor_access_finalized_field.cpp:18:9: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
7 destructor_access_finalized_field.cpp:19:5: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
13 destructor_access_finalized_field.cpp:20:5: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
Ddestructor_eagerly_finalized.txt1 …cpp:26:5: warning: [blink-gc] Finalizer '~HeapObjectEagerFinalizedAlso' accesses eagerly finalized…
7 …cpp:27:5: warning: [blink-gc] Finalizer '~HeapObjectEagerFinalizedAlso' accesses eagerly finalized…
/external/compiler-rt/lib/tsan/rtl/
Dtsan_flags.inc42 "Report races between atomic and plain memory accesses.")
66 "Per-thread history size, controls how many previous memory accesses "
68 "history_size=0 amounts to 32K memory accesses. Each next value doubles "
69 "the amount of memory accesses, up to history_size=7 that amounts to "
70 "4M memory accesses. The default value is 2 (128K memory accesses).")
/external/llvm/test/CodeGen/SystemZ/
Dunaligned-01.ll1 ; Check that unaligned accesses are allowed in general. We check the
25 ; Check that unaligned 2-byte accesses are allowed.
36 ; Check that unaligned 4-byte accesses are allowed.
50 ; Check that unaligned 8-byte accesses are allowed.
Dtls-02.ll1 ; Test initial-exec TLS accesses.
/external/selinux/python/sepolgen/src/sepolgen/
Daudit.py179 self.accesses = []
198 self.accesses.append(recs[i])
248 access_tuple = tuple( self.accesses)
254 … self.type, self.data = audit2why.analyze(scontext, tcontext, self.tclass, self.accesses);
264 raise ValueError("Invalid permission %s\n" % " ".join(self.accesses))
528 avc.accesses, avc, avc_type=avc.type, data=avc.data)
531 avc.accesses, avc, avc_type=avc.type, data=avc.data)
/external/llvm/test/CodeGen/X86/
Dslow-unaligned-mem.ll1 ; Intel chips with slow unaligned memory accesses
15 ; Intel chips with fast unaligned memory accesses
27 ; AMD chips with slow unaligned memory accesses
39 ; AMD chips with fast unaligned memory accesses
50 ; Other chips with slow unaligned memory accesses
58 ; Also verify that SSE4.2 or SSE4a imply fast unaligned accesses.
/external/selinux/python/sepolgen/tests/
Dtest_audit.py66 self.assertEqual(avc.accesses, [])
83 self.assertEqual(avc.accesses, ["getattr"])
106 self.assertEqual(avc.accesses, ["read"])
130 self.assertEqual(avc.accesses, ["dac_read_search"])
/external/fio/examples/
Drand-zones.fio2 # to have skewed random accesses. This example has 50% of the accesses
Djesd219.fio4 # the device the IO accesses will land. Based on posting from
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.c270 int accesses = 0; in qpu_num_sf_accesses() local
295 accesses++; in qpu_num_sf_accesses()
297 accesses++; in qpu_num_sf_accesses()
301 accesses++; in qpu_num_sf_accesses()
304 accesses++; in qpu_num_sf_accesses()
312 accesses++; in qpu_num_sf_accesses()
315 return accesses; in qpu_num_sf_accesses()
/external/arm-neon-tests/
DInitCache.s33 ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
34 ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
/external/llvm/test/Analysis/LoopAccessAnalysis/
Dnullptr.ll1 ; RUN: opt -loop-accesses -analyze %s | FileCheck %s
4 ; Test that the loop accesses are proven safe in this case.
Dindependent-interleaved.ll1 ; RUN: opt < %s -store-to-load-forwarding-conflict-detection=false -loop-accesses -analyze | FileCh…
4 ; This test checks that we prove the strided accesses to be independent before
Dnumber-of-memchecks.ll1 ; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
63 ; memory checks of accesses which differ by a constant value.
97 ; CHECK-NEXT: Grouped accesses:
152 ; accesses, so we cannot overflow the GEPs.
169 ; CHECK-NEXT: Grouped accesses:
248 ; CHECK-NEXT: Grouped accesses:
Dforward-loop-independent.ll1 ; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
14 ; MemoryDepChecker analysis for accesses of A.
Dreverse-memcheck-bounds.ll1 ; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
7 ; When generating checks for accesses with negative stride
/external/gemmlowp/doc/
Ddesign.txt11 complexity (n^3 vs. n^2), memory accesses are redundant (each matrix entry
14 accesses.
28 these accesses are redundant for the reason outlined above. The way that
30 so that most of these accesses hit the L1 cache, and most of the remaining
Ddesign.md8 complexity (n^3 vs. n^2), memory accesses are redundant (each matrix entry is
10 minimizing the inefficiency resulting from these redundant memory accesses.
24 accesses are redundant for the reason outlined above. The way that one minimizes
26 these accesses hit the L1 cache, and most of the remaining ones hit the L2
/external/deqp/doc/testspecs/GLES31/
Dfunctional.synchronization.txt44 accessed by other invocations. Image accesses are synchronized using
45 memoryBarrierImage(). SSBO accesses do not need to be explicitly synchronized
/external/swiftshader/third_party/LLVM/test/Analysis/TypeBasedAliasAnalysis/
Dfunctionattrs.ll40 ; that the function accesses memory through its arguments, which TBAA
58 ; Similar to the others, va_arg only accesses memory through its operand.
/external/deqp/external/vulkancts/modules/vulkan/renderpass/
DvktRenderPassMultisampleResolveTests.cpp1132 const tcu::ConstPixelBufferAccess accesses[] = in verify() local
1176 const Vec4 firstColor (accesses[0].getPixel(x, y)); in verify()
1193 const Vec4 color (accesses[attachmentNdx].getPixel(x, y)); in verify()
1218 …m_context.getTestContext().getLog() << tcu::LogImage(name.c_str(), name.c_str(), accesses[attachme… in verify()
1264 : accesses[0].getPixelUint(x, y)); in verify()
1284 const UVec4 color (accesses[attachmentNdx].getPixelUint(x, y)); in verify()
1303 …m_context.getTestContext().getLog() << tcu::LogImage(name.c_str(), name.c_str(), accesses[attachme… in verify()
1364 : accesses[0].getPixelInt(x, y)); in verify()
1391 …m_context.getTestContext().getLog() << tcu::LogImage(name.c_str(), name.c_str(), accesses[attachme… in verify()
/external/valgrind/helgrind/
DREADME_MSMProp2.txt146 later-observed accesses: either (1) the accessing thread holds at
147 least one lock in common with LS, or (2) those accesses must
151 Hence a Write state places a constraint on all accesses.

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