| /external/llvm/test/Assembler/ |
| D | atomic.ll | 16 ; CHECK: cmpxchg volatile i32* %x, i32 0, i32 1 acq_rel acquire
17 cmpxchg volatile i32* %x, i32 0, i32 1 acq_rel acquire
18 ; CHECK: cmpxchg i32* %x, i32 42, i32 0 acq_rel monotonic
19 cmpxchg i32* %x, i32 42, i32 0 acq_rel monotonic
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| /external/llvm/test/Bitcode/ |
| D | cmpxchg-upgrade.ll | 17 cmpxchg i32* %addr, i32 42, i32 0 acq_rel
18 ; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acq_rel acquire
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| D | atomic.ll | 11 cmpxchg weak i32* %addr, i32 %desired, i32 %new acq_rel acquire
12 ; CHECK: cmpxchg weak i32* %addr, i32 %desired, i32 %new acq_rel acquire
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| D | memInstructions.3.2.ll | 278 ; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
280 %res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
282 ; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
284 %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
286 ; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acqui…
288 %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
290 …T: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
292 %res16 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
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| D | use-list-order2.ll | 45 %cmpxchg.1 = cmpxchg i32* %word, i32 0, i32 2 acq_rel monotonic
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| D | compatibility-3.6.ll | 542 %cmpxchg.1 = cmpxchg i32* %word, i32 0, i32 5 acq_rel monotonic
543 ; CHECK: %cmpxchg.1 = cmpxchg i32* %word, i32 0, i32 5 acq_rel monotonic
582 fence acq_rel
583 ; CHECK: fence acq_rel
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| /external/llvm/test/Instrumentation/ThreadSanitizer/ |
| D | atomic.ll | 239 atomicrmw xchg i8* %a, i8 0 acq_rel, !dbg !7
247 atomicrmw add i8* %a, i8 0 acq_rel, !dbg !7
255 atomicrmw sub i8* %a, i8 0 acq_rel, !dbg !7
263 atomicrmw and i8* %a, i8 0 acq_rel, !dbg !7
271 atomicrmw or i8* %a, i8 0 acq_rel, !dbg !7
279 atomicrmw xor i8* %a, i8 0 acq_rel, !dbg !7
287 atomicrmw nand i8* %a, i8 0 acq_rel, !dbg !7
375 cmpxchg i8* %a, i8 0, i8 1 acq_rel acquire, !dbg !7
623 atomicrmw xchg i16* %a, i16 0 acq_rel, !dbg !7
631 atomicrmw add i16* %a, i16 0 acq_rel, !dbg !7
[all …]
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| /external/llvm/include/llvm/Support/ |
| D | AtomicOrdering.h | 34 acq_rel = 4, enumerator
145 /* acq_rel */ AtomicOrderingCABI::acq_rel, in toCABI()
|
| /external/swiftshader/third_party/LLVM/test/Assembler/ |
| D | atomic.ll | 15 ; CHECK: cmpxchg volatile i32* %x, i32 0, i32 1 acq_rel
16 cmpxchg volatile i32* %x, i32 0, i32 1 acq_rel
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | private-memory-atomics.ll | 15 %tmp4 = atomicrmw add i32* %tmp3, i32 7 acq_rel
28 %tmp4 = cmpxchg i32* %tmp3, i32 0, i32 1 acq_rel monotonic
|
| /external/llvm/test/CodeGen/X86/ |
| D | barrier-sse.ll | 10 fence acq_rel
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| D | atomic_idempotent.ll | 54 %1 = atomicrmw and i32* %p, i32 -1 acq_rel
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | atomic-fence-02.ll | 11 fence acq_rel
|
| /external/compiler-rt/lib/tsan/tests/unit/ |
| D | tsan_clock_test.cc | 50 vector.acq_rel(&cache, &chunked); in TEST()
279 void acq_rel(SimpleSyncClock *dst) { in acq_rel() function
349 thr0[tid]->acq_rel(sync0[cid]); in ClockFuzzer()
350 thr1[tid]->acq_rel(&cache, sync1[cid]); in ClockFuzzer()
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | barrier-sse.ll | 9 fence acq_rel
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | atomics.ll | 96 %val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire
127 %val = atomicrmw xchg i32* %mem, i32 %operand acq_rel
|
| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_clock.h | 109 void acq_rel(ClockCache *c, SyncClock *dst);
|
| D | tsan_clock.cc | 256 void ThreadClock::acq_rel(ClockCache *c, SyncClock *dst) { in acq_rel() function in __tsan::ThreadClock
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | cmpxchg-idioms.ll | 52 %pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic
|
| D | arm64-atomic.ll | 53 %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic
100 %val = atomicrmw nand i64* %p, i64 7 acq_rel
|
| /external/llvm/test/CodeGen/ARM/ |
| D | cmpxchg-idioms.ll | 73 %pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | nacl-atomic-errors.ll | 23 ;;; Check unexpected memory order parameter (release=4 and acq_rel=5
54 ;;; consume=2, acquire=3, acq_rel=5 are disallowed
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| /external/llvm/test/CodeGen/XCore/ |
| D | atomic.ll | 13 fence acq_rel
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| /external/llvm/utils/vim/syntax/ |
| D | llvm.vim | 40 \ acq_rel
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 420 case llvm::AtomicOrderingCABI::acq_rel: in emitAtomicCmpXchgFailureSet()
1050 case llvm::AtomicOrderingCABI::acq_rel: in EmitAtomicExpr()
1120 SI->addCase(Builder.getInt32((int)llvm::AtomicOrderingCABI::acq_rel), in EmitAtomicExpr()
|