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Searched refs:addImm (Results 1 – 25 of 212) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
101 .addImm(0); in lowerSubvectorStore()
[all …]
DSystemZInstrInfo.cpp175 MachineInstrBuilder(MF, Ear1MI).addImm(0); in expandLoadStackGuard()
181 MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32); in expandLoadStackGuard()
187 MachineInstrBuilder(MF, Ear2MI).addImm(1); in expandLoadStackGuard()
191 MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0); in expandLoadStackGuard()
222 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate); in emitGRX32Move()
421 .addImm(CCValid).addImm(CCMask).addMBB(TBB); in InsertBranch()
602 .addImm(CCValid) in PredicateInstruction()
603 .addImm(CCMask) in PredicateInstruction()
612 .addImm(CCValid) in PredicateInstruction()
613 .addImm(CCMask) in PredicateInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.cpp138 .addImm(UsedRegMask); in HandleVRSaveUpdate()
142 .addImm(UsedRegMask); in HandleVRSaveUpdate()
147 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
151 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
156 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
160 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
164 .addImm(UsedRegMask & 0xFFFF); in HandleVRSaveUpdate()
318 .addImm(FPOffset/4) in emitPrologue()
324 .addImm(LROffset / 4) in emitPrologue()
333 .addImm(FPOffset) in emitPrologue()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp339 .addImm(0) // ADDR in MakeFetchClause()
340 .addImm(AluInstCount - 1); // COUNT in MakeFetchClause()
388 .addImm(LiteralPair0) in insertLiterals()
389 .addImm(LiteralPair1); in insertLiterals()
431 MILit.addImm(Literals[i]->getImm()); in MakeALUClause()
438 MILit.addImm(Literals[i + 1]->getImm()); in MakeALUClause()
444 MILit.addImm(0); in MakeALUClause()
459 .addImm(CfCount); in EmitFetchClause()
473 .addImm(CfCount); in EmitALUClause()
541 .addImm(CfCount + 1) in runOnMachineFunction()
[all …]
DR600ISelLowering.cpp307 .addImm(isEOP(I)); // Set End of program bit in EmitInstrWithCustomInserter()
315 .addImm(isEOP(I)); // Set End of program bit in EmitInstrWithCustomInserter()
360 .addImm(SrcX) in EmitInstrWithCustomInserter()
361 .addImm(SrcY) in EmitInstrWithCustomInserter()
362 .addImm(SrcZ) in EmitInstrWithCustomInserter()
363 .addImm(SrcW) in EmitInstrWithCustomInserter()
364 .addImm(0) in EmitInstrWithCustomInserter()
365 .addImm(0) in EmitInstrWithCustomInserter()
366 .addImm(0) in EmitInstrWithCustomInserter()
367 .addImm(0) in EmitInstrWithCustomInserter()
[all …]
DR600EmitClauseMarkers.cpp283 .addImm(Address++) // ADDR in MakeALUClause()
284 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0 in MakeALUClause()
285 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1 in MakeALUClause()
286 .addImm(KCacheBanks.empty()?0:2) // KM0 in MakeALUClause()
287 .addImm((KCacheBanks.size() < 2)?0:2) // KM1 in MakeALUClause()
288 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0 in MakeALUClause()
289 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1 in MakeALUClause()
290 .addImm(AluInstCount) // COUNT in MakeALUClause()
291 .addImm(1); // Enabled in MakeALUClause()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrBuilder.h94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
138 MIB.addImm(AM.Disp); in addFullAddress()
178 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist); in emitPrologue()
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist); in emitPrologue()
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitPrologue()
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
127 .addImm(0).addReg(Alpha::R15); in emitEpilogue()
132 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitEpilogue()
136 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitEpilogue()
138 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitEpilogue()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
162 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
166 MIB.addImm(AM.Disp); in addFullAddress()
205 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUFrameLowering.cpp124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) in emitPrologue()
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) in emitPrologue()
132 .addImm(FrameSize); in emitPrologue()
137 .addImm(-16) in emitPrologue()
140 .addImm(FrameSize); in emitPrologue()
149 .addImm(16); in emitPrologue()
209 .addImm(FrameSize + LinkSlotOffset) in emitEpilogue()
213 .addImm(FrameSize); in emitEpilogue()
218 .addImm(16) in emitEpilogue()
221 .addImm(FrameSize); in emitEpilogue()
[all …]
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp164 .addImm(ARMCC::AL) in runOnMachineFunction()
1074 .addImm(ARMCC::AL) in EmitJumpTableInsts()
1314 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1330 .addImm(MI->getOperand(2).getImm()) in EmitInstruction()
1341 .addImm(ARMCC::AL) in EmitInstruction()
1377 .addImm(ARMCC::AL).addReg(0) in EmitInstruction()
1386 .addImm(ARMCC::AL) in EmitInstruction()
1395 .addImm(ARMCC::AL) in EmitInstruction()
1406 .addImm(ARMCC::AL) in EmitInstruction()
1419 .addImm(ARMCC::AL) in EmitInstruction()
[all …]
DARMExpandPseudoInsts.cpp578 MIB.addImm(Lane); in ExpandLaneOp()
692 LO16 = LO16.addImm(SOImmValV1); in ExpandMOV32BitImm()
693 HI16 = HI16.addImm(SOImmValV2); in ExpandMOV32BitImm()
696 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
697 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
723 LO16 = LO16.addImm(Lo16); in ExpandMOV32BitImm()
724 HI16 = HI16.addImm(Hi16); in ExpandMOV32BitImm()
745 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
746 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
796 MIB.addImm(0); in ExpandCMP_SWAP()
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiFrameLowering.cpp81 .addImm(MaxCallFrameSize); in replaceAdjDynAllocPseudo()
117 .addImm(-4) in emitPrologue()
118 .addImm(LPAC::makePreOp(LPAC::ADD)) in emitPrologue()
125 .addImm(8) in emitPrologue()
133 .addImm(StackSize) in emitPrologue()
189 .addImm(0); in emitEpilogue()
194 .addImm(-8) in emitEpilogue()
195 .addImm(LPAC::ADD); in emitEpilogue()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.cpp113 .addImm(0); in copyPhysReg()
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0); in copyPhysReg()
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); in copyPhysReg()
183 .addImm(0); in storeRegToStackSlot()
191 .addImm(0); in storeRegToStackSlot()
199 .addImm(0); in storeRegToStackSlot()
228 .addImm(0); in loadRegFromStackSlot()
235 .addImm(0); in loadRegFromStackSlot()
242 .addImm(0); in loadRegFromStackSlot()
/external/llvm/lib/Target/PowerPC/
DPPCBranchSelector.cpp202 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2); in runOnMachineFunction()
205 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
208 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
210 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
212 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
214 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
216 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); in runOnMachineFunction()
DPPCFrameLowering.cpp353 .addImm(UsedRegMask); in HandleVRSaveUpdate()
357 .addImm(UsedRegMask); in HandleVRSaveUpdate()
362 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
366 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
371 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
375 .addImm(UsedRegMask >> 16); in HandleVRSaveUpdate()
379 .addImm(UsedRegMask & 0xFFFF); in HandleVRSaveUpdate()
855 .addImm(8) in emitPrologue()
884 .addImm(FPOffset) in emitPrologue()
891 .addImm(PBPOffset) in emitPrologue()
[all …]
DPPCRegisterInfo.cpp388 .addImm(FrameSize); in lowerDynamicAlloc()
391 .addImm(0) in lowerDynamicAlloc()
395 .addImm(0) in lowerDynamicAlloc()
412 .addImm(~(MaxAlign-1)); in lowerDynamicAlloc()
428 .addImm(maxCallFrameSize); in lowerDynamicAlloc()
437 .addImm(~(MaxAlign-1)); in lowerDynamicAlloc()
453 .addImm(maxCallFrameSize); in lowerDynamicAlloc()
477 .addImm(maxCallFrameSize); in lowerDynamicAreaOffset()
521 .addImm(getEncodingValue(SrcReg) * 4) in lowerCRSpilling()
522 .addImm(0) in lowerCRSpilling()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeFrameLowering.cpp258 .addFrameIndex(FI).addImm(0); in interruptFrameLayout()
266 .addFrameIndex(R17FI).addImm(0); in interruptFrameLayout()
269 .addFrameIndex(R18FI).addImm(0); in interruptFrameLayout()
277 .addFrameIndex(MSRFI).addImm(0); in interruptFrameLayout()
280 .addFrameIndex(MSRFI).addImm(0); in interruptFrameLayout()
287 .addFrameIndex(R18FI).addImm(0); in interruptFrameLayout()
290 .addFrameIndex(R17FI).addImm(0); in interruptFrameLayout()
296 .addFrameIndex(VFI[--i]).addImm(0); in interruptFrameLayout()
368 .addReg(MBlaze::R1).addImm(-StackSize); in emitPrologue()
373 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset); in emitPrologue()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp123 .addImm(Encoding); in tryOrrMovk()
133 .addImm(Imm16) in tryOrrMovk()
134 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryOrrMovk()
190 .addImm(Encoding); in tryToreplicateChunks()
211 .addImm(Imm16) in tryToreplicateChunks()
212 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
235 .addImm(Imm16) in tryToreplicateChunks()
236 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
373 .addImm(Encoding); in trySequenceOfOnes()
385 .addImm(getChunk(UImm, FirstMovkIdx)) in trySequenceOfOnes()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreRegisterInfo.cpp149 .addImm(Amount); in eliminateCallFramePseudoInstr()
154 .addImm(Amount); in eliminateCallFramePseudoInstr()
262 .addImm(Offset); in eliminateFrameIndex()
268 .addImm(Offset); in eliminateFrameIndex()
273 .addImm(Offset); in eliminateFrameIndex()
290 .addImm(Offset); in eliminateFrameIndex()
296 .addImm(Offset); in eliminateFrameIndex()
301 .addImm(Offset); in eliminateFrameIndex()
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); in loadConstant()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp262 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
264 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
407 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
410 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
413 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
416 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
419 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
424 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
445 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
448 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp609 .addImm(Off); in splitMemRef()
612 .addImm(Off+4); in splitMemRef()
618 .addImm(Off) in splitMemRef()
622 .addImm(Off+4) in splitMemRef()
636 .addImm(Inc); in splitMemRef()
678 .addImm(int32_t(V & 0xFFFFFFFFULL)); in splitImmediate()
680 .addImm(int32_t(V >> 32)); in splitImmediate()
699 .addImm(Op1.getImm()); in splitCombine()
708 .addImm(Op2.getImm()); in splitCombine()
734 .addImm(31); in splitExt()
[all …]
DHexagonCopyToCombine.cpp633 .addImm(V); in emitConst64()
648 .addImm(LoOperand.getImm()); in emitCombineII()
653 .addImm(HiOperand.getImm()) in emitCombineII()
664 .addImm(LoOperand.getImm()); in emitCombineII()
669 .addImm(HiOperand.getImm()) in emitCombineII()
679 .addImm(LoOperand.getImm()); in emitCombineII()
684 .addImm(HiOperand.getImm()) in emitCombineII()
694 .addImm(LoOperand.getImm()); in emitCombineII()
699 .addImm(HiOperand.getImm()) in emitCombineII()
710 .addImm(HiOperand.getImm()) in emitCombineII()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrBuilder.h62 return MIB.addReg(Reg).addImm(0).addReg(0); in addDirectMem()
67 return MIB.addImm(Offset).addReg(0); in addOffset()
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0) in addRegReg()
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg); in addFullAddress()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrInfo.cpp195 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); in AnalyzeBranch()
237 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
239 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
296 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
299 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
302 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) in storeRegToStackSlot()
317 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
319 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
321 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()

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