Home
last modified time | relevance | path

Searched refs:addOperand (Results 1 – 25 of 228) sorted by relevance

12345678910

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMAsmPrinter.cpp984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); in EmitJump2Table()
985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitJump2Table()
986 BrInst.addOperand(MCOperand::CreateReg(0)); in EmitJump2Table()
1031 Inst.addOperand(MCOperand::CreateReg(Dest)); in populateADROperands()
1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); in populateADROperands()
1034 Inst.addOperand(MCOperand::CreateImm(pred)); in populateADROperands()
1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); in populateADROperands()
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); in EmitInstruction()
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
[all …]
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp577 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
583 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
622 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1742 Inst.addOperand(MCOperand::createImm(0)); in addExpr()
1744 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
1746 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1763 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1768 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocNumOperands()
1773 Inst.addOperand(MCOperand::createImm(getCoproc())); in addCoprocRegOperands()
1778 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); in addCoprocOptionOperands()
1783 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); in addITMaskOperands()
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp557 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
562 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
567 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
572 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
591 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
596 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
606 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
611 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
616 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); in addRegVSSRCOperands()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp538 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
539 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
546 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
548 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
558 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
559 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
564 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp222 CompoundInsn->addOperand(Rt); in getCompoundInsn()
223 CompoundInsn->addOperand(L.getOperand(1)); // Immediate in getCompoundInsn()
224 CompoundInsn->addOperand(R.getOperand(0)); // Jump target in getCompoundInsn()
234 CompoundInsn->addOperand(Rt); in getCompoundInsn()
235 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. in getCompoundInsn()
248 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 CompoundInsn->addOperand(Rt); in getCompoundInsn()
250 CompoundInsn->addOperand(R.getOperand(1)); in getCompoundInsn()
261 CompoundInsn->addOperand(Rs); in getCompoundInsn()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp271 Inst.addOperand(Reg); in HexagonProcessInstruction()
272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
273 Inst.addOperand(S16); in HexagonProcessInstruction()
290 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
291 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
309 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
322 MappedInst.addOperand(Ps); in HexagonProcessInstruction()
385 TmpInst.addOperand(MappedInst.getOperand(0)); in HexagonProcessInstruction()
386 TmpInst.addOperand(MappedInst.getOperand(1)); in HexagonProcessInstruction()
[all …]
DHexagonOptAddrMode.cpp320 MIB.addOperand(OldMI->getOperand(0)); in changeLoad()
321 MIB.addOperand(OldMI->getOperand(2)); in changeLoad()
322 MIB.addOperand(OldMI->getOperand(3)); in changeLoad()
323 MIB.addOperand(ImmOp); in changeLoad()
330 .addOperand(OldMI->getOperand(0)); in changeLoad()
346 MIB.addOperand(OldMI->getOperand(0)); in changeLoad()
347 MIB.addOperand(OldMI->getOperand(1)); in changeLoad()
348 MIB.addOperand(ImmOp); in changeLoad()
357 MIB.addOperand(OldMI->getOperand(i)); in changeLoad()
377 MIB.addOperand(OldMI->getOperand(1)); in changeStore()
[all …]
/external/llvm/include/llvm/MC/
DMCInstBuilder.h33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
63 Inst.addOperand(Op); in addOperand()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstrBuilder.h61 MI->addOperand(MachineOperand::CreateReg(RegNo,
76 MI->addOperand(MachineOperand::CreateImm(Val)); in addImm()
81 MI->addOperand(MachineOperand::CreateCImm(Val)); in addCImm()
86 MI->addOperand(MachineOperand::CreateFPImm(Val)); in addFPImm()
92 MI->addOperand(MachineOperand::CreateMBB(MBB, TargetFlags));
97 MI->addOperand(MachineOperand::CreateFI(Idx)); in addFrameIndex()
104 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
110 MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags));
117 MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags));
123 MI->addOperand(MachineOperand::CreateES(FnName, TargetFlags));
[all …]
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
245 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
274 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
284 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
295 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h73 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
88 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
93 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
98 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
104 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
109 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
116 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
122 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
129 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
136 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.cpp39 NopInst.addOperand(MCOperand::createImm(0)); in getNoopForMachoTarget()
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget()
41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
DARMExpandPseudoInsts.cpp100 UseMI.addOperand(MO); in TransferImpOps()
102 DefMI.addOperand(MO); in TransferImpOps()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
443 MIB.addOperand(MO); in ExpandVLD()
470 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVST()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp435 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
436 MOVI.addOperand(MCOperand::createImm(0)); in EmitFMov0()
444 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
445 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
449 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
450 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
503 TmpInst.addOperand(Dest); in EmitInstruction()
527 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
528 Adrp.addOperand(SymTLSDesc); in EmitInstruction()
[all …]
/external/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp126 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
178 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
180 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
190 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
192 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
202 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
204 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
222 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
229 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); in tryAddingSymbolicOperand()
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); in tryAddingSymbolicOperand()
529 MI.addOperand(MCOperand::CreateExpr(Expr)); in tryAddingSymbolicOperand()
857 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPRRegisterClass()
901 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodetcGPRRegisterClass()
928 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeSPRRegisterClass()
949 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeDPRRegisterClass()
983 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeQPRRegisterClass()
993 Inst.addOperand(MCOperand::CreateImm(Val)); in DecodePredicateOperand()
995 Inst.addOperand(MCOperand::CreateReg(0)); in DecodePredicateOperand()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp919 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
921 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
923 Inst.addOperand(MCOperand::CreateExpr(Expr)); in addExpr()
928 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
930 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
935 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocNumOperands()
940 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocRegOperands()
945 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); in addCoprocOptionOperands()
950 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); in addITMaskOperands()
955 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addITCondCodeOperands()
[all …]
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp170 MI.addOperand(MCOperand::createInst(Inst)); in getInstruction()
309 MI.addOperand(OPLow); in getSingleInstruction()
310 MI.addOperand(OPHigh); in getSingleInstruction()
476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); in DecodeRegisterClass()
578 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegsRegisterClass()
602 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegs64RegisterClass()
620 Inst.addOperand(MCOperand::createReg(Register)); in DecodeModRegsRegisterClass()
878 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial()
903 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial()
928 MI.addOperand(MCOperand::createImm(Value)); in decodeSpecial()
[all …]
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp354 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
359 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
368 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
374 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
558 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds4_6ImmOperands()
565 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds3_6ImmOperands()
759 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
766 NewInst.addOperand(I); in canonicalizeImmediates()
826 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
855 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp887 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
911 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
942 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeGPRPairRegisterClass()
972 Inst.addOperand(MCOperand::createReg(Register)); in DecodetcGPRRegisterClass()
1007 Inst.addOperand(MCOperand::createReg(Register)); in DecodeSPRRegisterClass()
1033 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPRRegisterClass()
1067 Inst.addOperand(MCOperand::createReg(Register)); in DecodeQPRRegisterClass()
1086 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPairRegisterClass()
1109 Inst.addOperand(MCOperand::createReg(Register)); in DecodeDPairSpacedRegisterClass()
1119 Inst.addOperand(MCOperand::createImm(Val)); in DecodePredicateOperand()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86MCInstLower.cpp225 OutMI.addOperand(OutMI.getOperand(0)); in LowerUnaryToTwoAddr()
226 OutMI.addOperand(OutMI.getOperand(0)); in LowerUnaryToTwoAddr()
247 Inst.addOperand(Saved); in SimplifyShortImmForm()
298 Inst.addOperand(Saved); in SimplifyShortMoveForm()
340 OutMI.addOperand(MCOp); in Lower()
401 OutMI.addOperand(Saved); in Lower()
427 OutMI.addOperand(Saved); in Lower()
551 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest in LowerTlsAddr()
552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base in LowerTlsAddr()
553 LEA.addOperand(MCOperand::CreateImm(1)); // scale in LowerTlsAddr()
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86Operand.h380 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
382 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
387 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
418 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
431 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
432 Inst.addOperand(MCOperand::createImm(getMemScale())); in addMemOperands()
433 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
435 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
442 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addAbsMemOperands()
444 Inst.addOperand(MCOperand::createExpr(getMemDisp())); in addAbsMemOperands()
[all …]
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp272 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
301 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
322 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
343 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
364 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
385 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
397 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
418 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
431 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32spRegisterClass()
452 Inst.addOperand(MCOperand::createReg(Register)); in DecodeVectorRegisterClass()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86Disassembler.cpp161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
256 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
426 mcInst.addOperand(baseReg); in translateRMMemory()
427 mcInst.addOperand(scaleAmount); in translateRMMemory()
428 mcInst.addOperand(indexReg); in translateRMMemory()
429 mcInst.addOperand(displacement); in translateRMMemory()
430 mcInst.addOperand(segmentReg); in translateRMMemory()
[all …]

12345678910