| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 282 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg)); in BuildSchedGraph()
293 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias)); in BuildSchedGraph()
331 UseSU->addPred(dep); in BuildSchedGraph()
344 UseSU->addPred(dep); in BuildSchedGraph()
374 ExitSU.addPred(SDep(SU, SDep::Order, Latency, in BuildSchedGraph()
429 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
434 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
440 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
447 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0)); in BuildSchedGraph()
450 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency)); in BuildSchedGraph()
[all …]
|
| D | ScheduleDAG.cpp | 88 bool SUnit::addPred(const SDep &D) { in addPred() function in SUnit
|
| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 318 UseSU->addPred(Dep); in addPhysRegDataDeps()
349 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); in addPhysRegDeps()
354 DefSU->addPred(Dep); in addPhysRegDeps()
465 UseSU->addPred(Dep); in addVRegDefDeps()
507 DefSU->addPred(Dep); in addVRegDefDeps()
549 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
628 SUb->addPred(Dep); in addChainDependency()
998 ExitSU.addPred(Dep); in buildSchedGraph()
|
| D | MachinePipeliner.cpp | 1028 SU.addPred(SDep(Load, SDep::Barrier)); in addLoopCarriedDependences()
1034 SU.addPred(SDep(Load, SDep::Barrier)); in addLoopCarriedDependences()
1041 SU.addPred(SDep(Load, SDep::Barrier)); in addLoopCarriedDependences()
1047 SU.addPred(SDep(Load, SDep::Barrier)); in addLoopCarriedDependences()
1052 SU.addPred(SDep(Load, SDep::Barrier)); in addLoopCarriedDependences()
1062 SU.addPred(SDep(Load, SDep::Barrier)); in addLoopCarriedDependences()
1104 I.addPred(Dep); in updatePhiDependences()
1110 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
1125 I.addPred(Dep); in updatePhiDependences()
1131 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
[all …]
|
| D | ScheduleDAG.cpp | 65 bool SUnit::addPred(const SDep &D, bool Required) { in addPred() function in SUnit
|
| D | MachineScheduler.cpp | 545 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial()); in addEdge()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 397 bool addPred(const SDep &D, bool Required = true);
407 return addPred(Dep);
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.h | 112 void addPred(SIScheduleBlock *Pred);
|
| D | SIMachineScheduler.cpp | 515 void SIScheduleBlock::addPred(SIScheduleBlock *Pred) { in addPred() function in SIScheduleBlock
1084 CurrentBlocks[SUID]->addPred(CurrentBlocks[Node2CurrentBlock[Pred->NodeNum]]); in createBlocksForVariant()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 353 bool addPred(const SDep &D);
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| D | ObjCARCOpts.cpp | 310 void addPred(BasicBlock *Pred) { Preds.push_back(Pred); } in addPred() function in __anon18bb0acc0111::BBState
1399 SuccStates.addPred(CurrBB); in ComputePostOrders()
1406 BBStates[SuccBB].addPred(CurrBB); in ComputePostOrders()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier)); in postprocessDAG()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 83 SU->addPred(D); in AddPred()
|
| D | ScheduleDAGSDNodes.cpp | 455 if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
|
| D | ScheduleDAGRRList.cpp | 205 SU->addPred(D); in AddPred()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 89 SU->addPred(D); in AddPred()
|
| D | ScheduleDAGSDNodes.cpp | 494 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
|
| D | ScheduleDAGRRList.cpp | 201 SU->addPred(D); in AddPred()
|