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Searched refs:addsub (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dsse3-intrinsics-x86.ll5 …%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x doub…
8 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
13 …%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>>…
16 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dsse3-intrinsics-fast-isel.ll17 %res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)
20 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
32 %res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)
35 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dsse_reload_fold.ll18 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
25 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
71 %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f)
106 %t = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %y, <2 x double> %f)
Dsse3-avx-addsub-2.ll5 ; Verify that we correctly generate 'addsub' instructions from
247 ; Verify that we don't generate addsub instruction for the following
Dstack-folding-fp-avx1.ll81 %2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)
84 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
90 %2 = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1)
93 declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
99 %2 = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)
102 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
108 %2 = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1)
111 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
Dstack-folding-fp-sse42.ll65 %2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1)
68 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
74 %2 = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1)
77 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
Davx-intrinsics-x86.ll1378 …%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x doub…
1381 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
1394 …%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>>…
1397 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
3175 …%res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x d…
3178 declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
3191 …%res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x floa…
3194 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
Davx-intrinsics-fast-isel.ll45 %res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1)
48 declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
60 %res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1)
63 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dsse_reload_fold.ll18 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
25 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
71 %t = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %y, <4 x float> %f)
106 %t = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %y, <2 x double> %f)
Davx-intrinsics-x86.ll847 …%res = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x doub…
850 declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) nounwind readnone
855 …%res = call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>>…
858 declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) nounwind readnone
1836 …%res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x d…
1839 declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
1844 …%res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x floa…
1847 declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
/external/llvm/lib/Target/Hexagon/
DHexagonBlockRanges.cpp106 void HexagonBlockRanges::RangeList::addsub(const IndexRange &A, in addsub() function in HexagonBlockRanges::RangeList
150 T.addsub(Rg, Range); in subtract()
DHexagonBlockRanges.h115 void addsub(const IndexRange &A, const IndexRange &B);
/external/llvm/test/Transforms/SLPVectorizer/X86/
Daddsub.ll15 ; CHECK-LABEL: @addsub
22 define void @addsub() #0 {
/external/swiftshader/third_party/LLVM/include/llvm/
DIntrinsics.gen131 x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
132 x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
390 x86_sse3_addsub_pd, // llvm.x86.sse3.addsub.pd
391 x86_sse3_addsub_ps, // llvm.x86.sse3.addsub.ps
658 "llvm.x86.avx.addsub.pd.256",
659 "llvm.x86.avx.addsub.ps.256",
917 "llvm.x86.sse3.addsub.pd",
918 "llvm.x86.sse3.addsub.ps",
4033 if (NameR.substr(7, 9) != ".addsub.p")
4038 return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub.pd"
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen4455 x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
4456 x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
5820 x86_sse3_addsub_pd, // llvm.x86.sse3.addsub.pd
5821 x86_sse3_addsub_ps, // llvm.x86.sse3.addsub.ps
10513 "llvm.x86.avx.addsub.pd.256",
10514 "llvm.x86.avx.addsub.ps.256",
11878 "llvm.x86.sse3.addsub.pd",
11879 "llvm.x86.sse3.addsub.ps",
18453 1, // llvm.x86.avx.addsub.pd.256
18454 1, // llvm.x86.avx.addsub.ps.256
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen4449 x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
4450 x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
5786 x86_sse3_addsub_pd, // llvm.x86.sse3.addsub.pd
5787 x86_sse3_addsub_ps, // llvm.x86.sse3.addsub.ps
10473 "llvm.x86.avx.addsub.pd.256",
10474 "llvm.x86.avx.addsub.ps.256",
11810 "llvm.x86.sse3.addsub.pd",
11811 "llvm.x86.sse3.addsub.ps",
18358 1, // llvm.x86.avx.addsub.pd.256
18359 1, // llvm.x86.avx.addsub.ps.256
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen4455 x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
4456 x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
5820 x86_sse3_addsub_pd, // llvm.x86.sse3.addsub.pd
5821 x86_sse3_addsub_ps, // llvm.x86.sse3.addsub.ps
10513 "llvm.x86.avx.addsub.pd.256",
10514 "llvm.x86.avx.addsub.ps.256",
11878 "llvm.x86.sse3.addsub.pd",
11879 "llvm.x86.sse3.addsub.ps",
18453 1, // llvm.x86.avx.addsub.pd.256
18454 1, // llvm.x86.avx.addsub.ps.256
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen4455 x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
4456 x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
5820 x86_sse3_addsub_pd, // llvm.x86.sse3.addsub.pd
5821 x86_sse3_addsub_ps, // llvm.x86.sse3.addsub.ps
10513 "llvm.x86.avx.addsub.pd.256",
10514 "llvm.x86.avx.addsub.ps.256",
11878 "llvm.x86.sse3.addsub.pd",
11879 "llvm.x86.sse3.addsub.ps",
18453 1, // llvm.x86.avx.addsub.pd.256
18454 1, // llvm.x86.avx.addsub.ps.256
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSSE.td5240 // Patterns used to select 'addsub' instructions.