/external/llvm/test/CodeGen/Hexagon/intrinsics/ |
D | cr.ll | 81 declare i32 @llvm.hexagon.C2.andn(i32, i32) 83 %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b) 95 declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32) 97 %z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c) 116 declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32) 118 %z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
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D | alu32_alu.ll | 51 declare i32 @llvm.hexagon.A4.andn(i32, i32) 53 %z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b)
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D | xtype_alu.ll | 240 declare i32 @llvm.hexagon.M4.or.andn(i32, i32, i32) 242 %z = call i32 @llvm.hexagon.M4.or.andn(i32 %a, i32 %b, i32 %c) 247 declare i32 @llvm.hexagon.M4.and.andn(i32, i32, i32) 249 %z = call i32 @llvm.hexagon.M4.and.andn(i32 %a, i32 %b, i32 %c) 254 declare i32 @llvm.hexagon.M4.xor.andn(i32, i32, i32) 256 %z = call i32 @llvm.hexagon.M4.xor.andn(i32 %a, i32 %b, i32 %c)
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/external/llvm/test/CodeGen/SPARC/ |
D | stack-align.ll | 8 ;; andn), that the local var is accessed via stack pointer (to %o0), and that 12 ;; CHECK: andn %sp, 63, %sp
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D | atomics.ll | 74 ; CHECK: andn %o3, %o1, %o1 84 ; CHECK: andn %g2, %o5, %g2 125 ; CHECK: andn %g2, %o5, %g2
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D | 64bit.ll | 115 ; CHECK: andn [[R1]], %i0, %i0
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/external/llvm/test/CodeGen/X86/ |
D | peep-test-4.ll | 137 ; CHECK-LABEL: andn: 142 define void @andn(i32 %x, i32 %y) nounwind { 144 %andn = and i32 %y, %not 145 %cmp = icmp eq i32 %andn, 0 149 tail call void @foo(i32 %andn)
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D | bmi.ll | 127 ; Don't choose a 'test' if an 'andn' can be used. 140 ; Recognize a disguised andn in the following 4 tests. 185 ; A mask and compare against constant is ok for an 'andn' too 199 ; But don't use 'andn' if the mask is a power-of-two. 212 ; Don't transform to 'andn' if there's another use of the 'and'. 254 ; Don't choose a 'test' if an 'andn' can be used. 267 ; Use a 'test' (not an 'and') because 'andn' only works for i32/i64.
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D | xor.ll | 180 ; X64: andn 182 ; X32: andn
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D | avx512dqvl-intrinsics.ll | 320 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 331 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 341 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 351 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 363 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 374 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 386 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 400 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 413 …%res = call <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float> %a, <4 x float> %b, <4 x flo… 417 declare <4 x float> @llvm.x86.avx512.mask.andn.ps.128(<4 x float>, <4 x float>, <4 x float>, i8) [all …]
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/external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
D | mblaze_typea.s | 34 # CHECK: andn 37 andn r1, r2, r3
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/external/llvm/test/MC/Sparc/ |
D | sparc-alu-instructions.s | 27 ! CHECK: andn %g1, %g2, %g3 ! encoding: [0x86,0x28,0x40,0x02] 28 andn %g1, %g2, %g3
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D | sparc-synthetic-instructions.s | 93 ! CHECK: andn %g2, %g1, %g2 ! encoding: [0x84,0x28,0x80,0x01] 95 ! CHECK: andn %g2, 4, %g2 ! encoding: [0x84,0x28,0xa0,0x04]
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/external/bison/lib/ |
D | bbitset.h | 136 void (*andn) (bitset, bitset, bitset); member 234 #define BITSET_ANDN_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn (DST, SRC1, SRC2)
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/external/mesa3d/src/mesa/sparc/ |
D | xform.S | 75 andn %g3, 1, %o2 147 andn %g3, 1, %o2 190 andn %g3, 1, %o2 244 andn %g3, 1, %o2 292 andn %g3, 1, %o2 355 andn %g3, 1, %o2 406 andn %g3, 1, %o2 532 andn %g3, 1, %o2 601 andn %g3, 1, %o2 659 andn %g3, 1, %o2 [all …]
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/ |
D | mblaze_typea.txt | 22 # CHECK: andn r1, r2, r3
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/external/llvm/test/MC/Disassembler/Sparc/ |
D | sparc.txt | 30 # CHECK: andn %g1, %g2, %g3
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/external/v8/src/ia32/ |
D | assembler-ia32.h | 1314 void andn(Register dst, Register src1, Register src2) { in andn() function 1315 andn(dst, src1, Operand(src2)); in andn() 1317 void andn(Register dst, Register src1, const Operand& src2) { in andn() function
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcInstrInfo.td | 428 "andn $b, $c, $dst", 432 "andn $b, $c, $dst", []>;
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrAliases.td | 418 // bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
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D | SparcInstr64Bit.td | 152 "andn $b, $c, $dst",
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D | SparcInstrInfo.td | 654 "andn $rs1, $rs2, $rd", 658 "andn $rs1, $simm13, $rd", []>;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrArithmetic.td | 1171 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V; 1172 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
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/external/llvm/lib/Target/X86/ |
D | X86InstrArithmetic.td | 1283 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V; 1284 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeInstrInfo.td | 363 def ANDN : ArithN<0x23, 0x000, "andn ", IIC_ALU>;
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