/external/llvm/test/MC/AArch64/ |
D | arm64-logical-encoding.s | 13 ands w0, w0, #1 14 ands x0, x0, #1 15 ands w1, w2, #15 16 ands x1, x2, #15 23 ; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72] 24 ; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2] 25 ; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72] 26 ; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2] 72 ands w1, w2, w3 73 ands x1, x2, x3 [all …]
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D | alias-logicalimm.s | 15 ands x0, x1, #~2 20 ands w0, w1, #~2
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-logical.txt | 23 # CHECK: ands w0, w0, #0x1 24 # CHECK: ands x0, x0, #0x1 25 # CHECK: ands w1, w2, #0xf 26 # CHECK: ands x1, x2, #0xf 82 # CHECK: ands w1, w2, w3 83 # CHECK: ands x1, x2, x3 84 # CHECK: ands w1, w2, w3, lsl #2 85 # CHECK: ands x1, x2, x3, lsl #2 86 # CHECK: ands w1, w2, w3, lsr #2 87 # CHECK: ands x1, x2, x3, lsr #2 [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | arm-and-tst-peephole.ll | 26 ; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 30 ; THUMB-NEXT: ands r[[R0]], r 34 ; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 81 ; ARM: ands 82 ; THUMB: ands 83 ; T2: ands 93 ; THUMB: ands
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D | 2011-04-15-AndVFlagPeepholeBug.ll | 4 ; CHECK-NOT: ands
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/external/llvm/test/CodeGen/ARM/ |
D | arm-and-tst-peephole.ll | 28 ; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 32 ; THUMB-NEXT: ands r[[R0]], r 36 ; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 95 ; ARM: ands 96 ; THUMB: ands 97 ; T2: ands 98 ; V8: ands 110 ; THUMB: ands 112 ; V8: ands
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D | 2011-04-15-AndVFlagPeepholeBug.ll | 4 ; CHECK-NOT: ands
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/external/libavc/encoder/arm/ |
D | ih264e_evaluate_intra4x4_modes_a9q.s | 154 ands r10, r8, #01 @VERT sad ?? 173 ands r10, r8, #02 @HORZ sad ?? 198 ands r10, r8, #04 @DC sad ?? 206 ands r10, r5, #1 209 ands r10, r5, #4 212 ands r10, r5, #5 234 ands r10, r8, #504 @/* if modes other than VERT, HORZ and DC are valid ????*/ 255 ands r10, r8, #0x08 @DIAG_DL sad ?? 284 ands r10, r8, #16 @DIAG_DR sad ?? 313 ands r10, r8, #32 @VERT_R sad ?? [all …]
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D | ih264e_evaluate_intra16x16_modes_a9q.s | 105 ands r7, r5, #01 109 ands r8, r5, #04 202 ands r7, r0, #01 @ vert mode valid???????????? 206 ands r6, r0, #02 @ horz mode valid???????????? 215 ands r6, r0, #04 @ dc mode valid????????????
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D | ih264e_evaluate_intra_chroma_modes_a9q.s | 264 ands r7, r0, #04 @ vert mode valid???????????? 267 ands r6, r0, #02 @ horz mode valid???????????? 270 ands r6, r0, #01 @ dc mode valid????????????
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/external/llvm/test/MC/ARM/ |
D | thumb_rewrites.s | 59 ands r0, r1, r0 60 @ CHECK: ands r0, r1 @ encoding: [0x08,0x40] 62 ands r0, r0, r1 63 @ CHECK: ands r0, r1 @ encoding: [0x08,0x40]
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D | arm_instructions.s | 25 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] 26 ands r1,r2,r3
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | arm_instructions.s | 18 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] 19 ands r1,r2,r3
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/external/valgrind/none/tests/arm64/ |
D | integer.stdout.exp | 293 ands x3,x4, #0x8080808080808080 :: rd 8000808000000000 rn 843fdf810277796e, cin 0, nzcv 80000000 N … 294 ands x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd c04040c080400000 rn c5446fe48c610b28, cin 0, nzcv 80000000 N … 295 ands x3,x4, #0x8080808080808080 :: rd 0000808000000000 rn 143fdf810277796e, cin 0, nzcv 00000000 … 296 ands x3,x4, #0xC0C0C0C0C0C0C0C0 :: rd 804040c080400000 rn a5446fe48c610b28, cin 0, nzcv 80000000 N … 297 ands x3,x4, #0x8080808080808080 :: rd 0000000000000000 rn 7070707070707070, cin 0, nzcv 40000000 Z… 298 ands x3,x4, #0x8080808080808080 :: rd 8000000000000000 rn f070707070707070, cin 0, nzcv 80000000 N … 302 ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 843fdf810277796e, cin 0, nzcv 40000000 Z 303 ands w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn c5446fe48c610b28, cin 0, nzcv 80000000 N 304 ands w3,w4, #0x80808080 :: rd 0000000000000000 rn 143fdf810277796e, cin 0, nzcv 40000000 Z 305 ands w3,w4, #0xC0C0C0C0 :: rd 0000000080400000 rn a5446fe48c610b28, cin 0, nzcv 80000000 N [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
D | mulhs.ll | 1 ; All of these ands and shifts should be folded into rlwimi's
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D | rlwinm2.ll | 1 ; All of these ands and shifts should be folded into rlw[i]nm instructions
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D | rlwimi2.ll | 1 ; All of these ands and shifts should be folded into rlwimi's
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/external/llvm/test/CodeGen/PowerPC/ |
D | mulhs.ll | 1 ; All of these ands and shifts should be folded into rlwimi's
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D | rlwinm2.ll | 1 ; All of these ands and shifts should be folded into rlw[i]nm instructions
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-fast-isel.ll | 95 define void @ands(i32* %addr) { 96 ; CHECK-LABEL: ands:
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/external/llvm/test/CodeGen/SystemZ/ |
D | risbg-02.ll | 96 ; ands with complement masks. 109 ; ands with incompatible masks.
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/external/libavc/encoder/armv8/ |
D | ih264e_evaluate_intra_chroma_modes_av8.s | 106 ands w6, w5, w19 380 ands w7, w0, #04 // vert mode valid???????????? 383 ands w6, w0, #02 // horz mode valid???????????? 386 ands w6, w0, #01 // dc mode valid????????????
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D | ih264e_evaluate_intra16x16_modes_av8.s | 110 ands w6, w5, #0x01 116 ands w6, w5, #0x04 476 ands w7, w0, #01 // vert mode valid???????????? 480 ands w6, w0, #02 // horz mode valid???????????? 483 ands w6, w0, #04 // dc mode valid????????????
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/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
D | thumb2-and.ll | 5 ; CHECK: ands r0, r1
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/external/llvm/test/CodeGen/Thumb2/ |
D | thumb2-and.ll | 5 ; CHECK: ands r0, r1
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