Searched refs:areMemAccessesTriviallyDisjoint (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| D | LanaiInstrInfo.cpp | 89 bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() function in LanaiInstrInfo
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| D | AArch64LoadStoreOptimizer.cpp | 1085 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
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| D | AArch64InstrInfo.cpp | 657 bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint( in areMemAccessesTriviallyDisjoint() function in AArch64InstrInfo
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| D | HexagonExpandCondsets.cpp | 824 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) in canMoveMemTo()
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| D | HexagonInstrInfo.cpp | 1626 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint( in areMemAccessesTriviallyDisjoint() function in HexagonInstrInfo
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 167 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| D | SIInstrInfo.cpp | 1364 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint() function in SIInstrInfo
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA)) in MIsNeedChainEdge()
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| D | MachinePipeliner.cpp | 1032 assert(TII->areMemAccessesTriviallyDisjoint(LdMI, MI, AA) && in addLoopCarriedDependences()
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