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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
47 def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
48 def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
95 def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;
96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
[all …]
DAArch64InstrInfo.td386 def : InstAlias<"nop", (HINT 0b000)>;
830 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
831 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
832 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
833 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
950 defm RBIT : OneOperandData<0b000, "rbit">;
1280 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1281 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1282 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
2495 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
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/external/valgrind/none/tests/ppc32/
Dtest_dfp2.stdout.exp_Without_dcffix10 dctdp 000400000089b000 D32->D64 => 20c400000009b000
27 dctdp 000400000089b000 D32->D64 => 20c400000009b000
44 dctdp 000400000089b000 D32->D64 => 20c400000009b000
61 dctdp 000400000089b000 D32->D64 => 20c400000009b000
78 dctdp 000400000089b000 D32->D64 => 20c400000009b000
95 dctdp 000400000089b000 D32->D64 => 20c400000009b000
112 dctdp 000400000089b000 D32->D64 => 20c400000009b000
129 dctdp 000400000089b000 D32->D64 => 20c400000009b000
147 drsp 000400000089b000 D64->D32 => 0000000000000000
164 drsp 000400000089b000 D64->D32 => 0000000000000000
[all …]
/external/valgrind/none/tests/ppc64/
Dtest_dfp2.stdout.exp_Without_dcffix10 dctdp 000400000089b000 D32->D64 => 20c400000009b000
27 dctdp 000400000089b000 D32->D64 => 20c400000009b000
44 dctdp 000400000089b000 D32->D64 => 20c400000009b000
61 dctdp 000400000089b000 D32->D64 => 20c400000009b000
78 dctdp 000400000089b000 D32->D64 => 20c400000009b000
95 dctdp 000400000089b000 D32->D64 => 20c400000009b000
112 dctdp 000400000089b000 D32->D64 => 20c400000009b000
129 dctdp 000400000089b000 D32->D64 => 20c400000009b000
147 drsp 000400000089b000 D64->D32 => 0000000000000000
164 drsp 000400000089b000 D64->D32 => 0000000000000000
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonSystemInst.td62 "dccleana($Rs)", [], 0b000, 0b000, 0b0>;
64 "dcinva($Rs)", [], 0b000, 0b000, 0b1>;
66 "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>;
72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
DHexagonInstrInfoV5.td60 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
65 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
173 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
174 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
177 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
189 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
211 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
272 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
277 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
607 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
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DHexagonInstrInfo.td188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
802 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
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DHexagonInstrEnc.td486 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
505 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
559 let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} };
573 let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} };
669 let Inst{13-0} = { src2{0}, 0b000, opc{3}, 0, opc{2-0}, dst{4-0} };
712 let Inst{13-0} = { src3{0}, src1{1-0}, 0b000, opc{2-0}, src4{4-0} };
765 let Inst{13-0} = { opc{2}, 0b000, src1{1-0}, opc{1-0}, 1, dst{4-0} };
860 let Inst{13-0} = { 0b0000, src1{1-0}, 0b000, opc{2-0}, dst{1-0} };
863 class V6_pred_and_enc : Enc_COPROC_VX_3op_q<0b000>;
908 let Inst{13-0} = { opc{2}, 0b000000, opc{1}, 0b000, opc{0}, dst{1-0} };
[all …]
DHexagonInstrInfoV4.td616 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
713 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
742 let Inst{13-11} = 0b000;
788 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
1020 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1624 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1684 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1976 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1982 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1987 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
[all …]
DHexagonInstrInfoVector.td75 def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>;
79 def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>;
/external/syslinux/memdisk/
De820data5 00000000000f5000 000000000000b000 2 9
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-SRS-arm.txt12 # Inst{7-5} = 0b000
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td397 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
398 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
399 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
400 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
417 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
418 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
419 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
420 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
422 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
423 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
[all …]
DMipsMSAInstrFormats.td438 let Inst{10-8} = 0b000;
452 let Inst{10-8} = 0b000;
DMicroMips32r6InstrFormats.td391 let Inst{8-6} = 0b000;
421 let Inst{8-6} = 0b000;
/external/libmtp/logs/
Dmtp-detect-samsung-yp-s3.txt59 0240: b400 005f b000 0065 6d00 0066 1c00 006b ..._...em..f...k
64 0290: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
70 02f0: b400 005f b000 0062 cf00 0066 1c00 006b ..._...b...f...k
86 03f0: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
124 0240: b400 005f b000 0065 6d00 0066 1c00 006b ..._...em..f...k
129 0290: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
135 02f0: b400 005f b000 0062 cf00 0066 1c00 006b ..._...b...f...k
151 03f0: be00 0053 7c00 0059 b400 005f b000 0065 ...S|..Y..._...e
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td513 let Inst{14-12} = 0b000; // imm3
591 let Inst{14-12} = 0b000; // imm3
680 let Inst{14-12} = 0b000; // imm3
721 let Inst{14-12} = 0b000; // imm3
843 let Inst{14-12} = 0b000; // imm3
1689 let Inst{14-12} = 0b000;
1783 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1789 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1825 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1902 let Inst{6-4} = 0b000;
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DARMInstrNEON.td3743 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3752 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3761 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3770 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3792 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3801 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3810 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3819 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3844 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3851 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
[all …]
DARMInstrThumb.td284 let Inst{2-0} = 0b000;
389 let Inst{2-0} = 0b000;
446 let Inst{2-0} = 0b000;
682 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td601 let Inst{14-12} = 0b000; // imm3
685 let Inst{14-12} = 0b000; // imm3
806 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
945 let Inst{14-12} = 0b000; // imm3
1421 let Inst{26-24} = 0b000;
1869 let Inst{14-12} = 0b000;
1973 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1979 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
2033 defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
[all …]
DARMInstrThumb.td338 let Inst{2-0} = 0b000;
456 let Inst{2-0} = 0b000;
520 let Inst{2-0} = 0b000;
742 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,
DARMInstrNEON.td4865 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4874 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4883 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4892 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4916 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4925 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4934 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4943 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4968 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4975 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
[all …]
/external/mesa3d/src/compiler/glsl/tests/
Darray_refcount_test.cpp665 operand b000 = deref_array( in TEST_F() local
692 deref_array(var_b, b000), in TEST_F()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_disasm.c352 [0b000] = "OWord Block Read",
361 [0b000] = "OWord block write",
416 [0b000] = "SIMD16",
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td317 defm ADD_ : ALUarith<0b000, "add", add, i32lo16z, i32hi16>;
350 defm ADD_F_ : ALUarith<0b000, "add.f", addc, i32lo16z, i32hi16>;
411 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),

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