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Searched refs:baseAlign (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/amd/addrlib/r800/
Dsiaddrlib.h132 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
164 UINT_32 baseAlign, UINT_32 pitchAlign,
191 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
Degbaddrlib.cpp233 &pOut->baseAlign, in ComputeSurfaceInfoLinear()
276 pOut->baseAlign, in ComputeSurfaceInfoLinear()
357 &pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
386 pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
449 &pOut->baseAlign, in ComputeSurfaceInfoMacroTiled()
508 &pOut->baseAlign, in ComputeSurfaceInfoMacroTiled()
1123 UINT_32 baseAlign; in HwlDegradeBaseLevel() local
1154 &baseAlign, in HwlDegradeBaseLevel()
3037 UINT_32 baseAlign ///< [in] base alignments in ComputeHtileBytes()
3116 pOut->baseAlign = surfOut.baseAlign; in DispatchComputeFmaskInfo()
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Degbaddrlib.h169 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
177 UINT_32 baseAlign, UINT_32 pitchAlign,
287 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
Dsiaddrlib.cpp777 UINT_32 baseAlign ///< [in] base alignments in HwlComputeHtileBytes()
780 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign); in HwlComputeHtileBytes()
1189 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentLinear() argument
1344 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentMicroTiled() argument
1364 while ((physicalSliceSize % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
1387 while ((logicalSiceSizeStencil % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
/external/mesa3d/src/amd/addrlib/core/
Daddrlib.cpp1475 &pOut->baseAlign); in ComputeHtileInfo()
1540 &pOut->baseAlign, in ComputeCmaskInfo()
1975 UINT_32 baseAlign; in ComputeHtileInfo() local
2003 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo); in ComputeHtileInfo()
2011 baseAlign); in ComputeHtileInfo()
2024 SafeAssign(pBaseAlign, baseAlign); in ComputeHtileInfo()
2045 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); in ComputeCmaskBaseAlign() local
2052 baseAlign *= pTileInfo->banks; in ComputeCmaskBaseAlign()
2056 return baseAlign; in ComputeCmaskBaseAlign()
2111 UINT_32 baseAlign; in ComputeCmaskInfo() local
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Daddrlib.h365 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
/external/mesa3d/src/amd/addrlib/
Daddrinterface.h531 UINT_32 baseAlign; ///< Base address alignment member
825 UINT_32 baseAlign; ///< Base alignment member
1036 UINT_32 baseAlign; ///< Base alignment member
1233 UINT_32 baseAlign; ///< Base address alignment member
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_surface.c192 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in compute_level()
265 surf->htile_alignment = AddrHtileOut->baseAlign; in compute_level()
508 surf->surf_alignment = AddrSurfInfoOut.baseAlign; in amdgpu_surface_init()
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.c203 surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign); in radv_compute_level()
467 surf->bo_alignment = AddrSurfInfoOut.baseAlign; in radv_amdgpu_winsys_surface_init()