1 /* 2 * Format of an instruction in memory. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 * Copyright (C) 2006 by Thiemo Seufer 10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 11 * Copyright (C) 2014 Imagination Technologies Ltd. 12 */ 13 #ifndef _UAPI_ASM_INST_H 14 #define _UAPI_ASM_INST_H 15 16 #include <asm/bitfield.h> 17 18 /* 19 * Major opcodes; before MIPS IV cop1x was called cop3. 20 */ 21 enum major_op { 22 spec_op, bcond_op, j_op, jal_op, 23 beq_op, bne_op, blez_op, bgtz_op, 24 addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op, 25 andi_op, ori_op, xori_op, lui_op, 26 cop0_op, cop1_op, cop2_op, cop1x_op, 27 beql_op, bnel_op, blezl_op, bgtzl_op, 28 daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op, 29 spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op, 30 lb_op, lh_op, lwl_op, lw_op, 31 lbu_op, lhu_op, lwr_op, lwu_op, 32 sb_op, sh_op, swl_op, sw_op, 33 sdl_op, sdr_op, swr_op, cache_op, 34 ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op, 35 lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op, 36 sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op, 37 scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op 38 }; 39 40 /* 41 * func field of spec opcode. 42 */ 43 enum spec_op { 44 sll_op, movc_op, srl_op, sra_op, 45 sllv_op, pmon_op, srlv_op, srav_op, 46 jr_op, jalr_op, movz_op, movn_op, 47 syscall_op, break_op, spim_op, sync_op, 48 mfhi_op, mthi_op, mflo_op, mtlo_op, 49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 50 mult_op, multu_op, div_op, divu_op, 51 dmult_op, dmultu_op, ddiv_op, ddivu_op, 52 add_op, addu_op, sub_op, subu_op, 53 and_op, or_op, xor_op, nor_op, 54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 55 dadd_op, daddu_op, dsub_op, dsubu_op, 56 tge_op, tgeu_op, tlt_op, tltu_op, 57 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 58 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 60 }; 61 62 /* 63 * func field of spec2 opcode. 64 */ 65 enum spec2_op { 66 madd_op, maddu_op, mul_op, spec2_3_unused_op, 67 msub_op, msubu_op, /* more unused ops */ 68 clz_op = 0x20, clo_op, 69 dclz_op = 0x24, dclo_op, 70 sdbpp_op = 0x3f 71 }; 72 73 /* 74 * func field of spec3 opcode. 75 */ 76 enum spec3_op { 77 ext_op, dextm_op, dextu_op, dext_op, 78 ins_op, dinsm_op, dinsu_op, dins_op, 79 yield_op = 0x09, lx_op = 0x0a, 80 lwle_op = 0x19, lwre_op = 0x1a, 81 cachee_op = 0x1b, sbe_op = 0x1c, 82 she_op = 0x1d, sce_op = 0x1e, 83 swe_op = 0x1f, bshfl_op = 0x20, 84 swle_op = 0x21, swre_op = 0x22, 85 prefe_op = 0x23, dbshfl_op = 0x24, 86 cache6_op = 0x25, sc6_op = 0x26, 87 scd6_op = 0x27, lbue_op = 0x28, 88 lhue_op = 0x29, lbe_op = 0x2c, 89 lhe_op = 0x2d, lle_op = 0x2e, 90 lwe_op = 0x2f, pref6_op = 0x35, 91 ll6_op = 0x36, lld6_op = 0x37, 92 rdhwr_op = 0x3b 93 }; 94 95 /* 96 * Bits 10-6 minor opcode for r6 spec mult/div encodings 97 */ 98 enum mult_op { 99 mult_mult_op = 0x0, 100 mult_mul_op = 0x2, 101 mult_muh_op = 0x3, 102 }; 103 enum multu_op { 104 multu_multu_op = 0x0, 105 multu_mulu_op = 0x2, 106 multu_muhu_op = 0x3, 107 }; 108 enum div_op { 109 div_div_op = 0x0, 110 div_div6_op = 0x2, 111 div_mod_op = 0x3, 112 }; 113 enum divu_op { 114 divu_divu_op = 0x0, 115 divu_divu6_op = 0x2, 116 divu_modu_op = 0x3, 117 }; 118 enum dmult_op { 119 dmult_dmult_op = 0x0, 120 dmult_dmul_op = 0x2, 121 dmult_dmuh_op = 0x3, 122 }; 123 enum dmultu_op { 124 dmultu_dmultu_op = 0x0, 125 dmultu_dmulu_op = 0x2, 126 dmultu_dmuhu_op = 0x3, 127 }; 128 enum ddiv_op { 129 ddiv_ddiv_op = 0x0, 130 ddiv_ddiv6_op = 0x2, 131 ddiv_dmod_op = 0x3, 132 }; 133 enum ddivu_op { 134 ddivu_ddivu_op = 0x0, 135 ddivu_ddivu6_op = 0x2, 136 ddivu_dmodu_op = 0x3, 137 }; 138 139 /* 140 * rt field of bcond opcodes. 141 */ 142 enum rt_op { 143 bltz_op, bgez_op, bltzl_op, bgezl_op, 144 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 145 tgei_op, tgeiu_op, tlti_op, tltiu_op, 146 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 147 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 148 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 149 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 150 bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op 151 }; 152 153 /* 154 * rs field of cop opcodes. 155 */ 156 enum cop_op { 157 mfc_op = 0x00, dmfc_op = 0x01, 158 cfc_op = 0x02, mfhc0_op = 0x02, 159 mfhc_op = 0x03, mtc_op = 0x04, 160 dmtc_op = 0x05, ctc_op = 0x06, 161 mthc0_op = 0x06, mthc_op = 0x07, 162 bc_op = 0x08, bc1eqz_op = 0x09, 163 mfmc0_op = 0x0b, bc1nez_op = 0x0d, 164 wrpgpr_op = 0x0e, cop_op = 0x10, 165 copm_op = 0x18 166 }; 167 168 /* 169 * rt field of cop.bc_op opcodes 170 */ 171 enum bcop_op { 172 bcf_op, bct_op, bcfl_op, bctl_op 173 }; 174 175 /* 176 * func field of cop0 coi opcodes. 177 */ 178 enum cop0_coi_func { 179 tlbr_op = 0x01, tlbwi_op = 0x02, 180 tlbwr_op = 0x06, tlbp_op = 0x08, 181 rfe_op = 0x10, eret_op = 0x18, 182 wait_op = 0x20, 183 }; 184 185 /* 186 * func field of cop0 com opcodes. 187 */ 188 enum cop0_com_func { 189 tlbr1_op = 0x01, tlbw_op = 0x02, 190 tlbp1_op = 0x08, dctr_op = 0x09, 191 dctw_op = 0x0a 192 }; 193 194 /* 195 * fmt field of cop1 opcodes. 196 */ 197 enum cop1_fmt { 198 s_fmt, d_fmt, e_fmt, q_fmt, 199 w_fmt, l_fmt 200 }; 201 202 /* 203 * func field of cop1 instructions using d, s or w format. 204 */ 205 enum cop1_sdw_func { 206 fadd_op = 0x00, fsub_op = 0x01, 207 fmul_op = 0x02, fdiv_op = 0x03, 208 fsqrt_op = 0x04, fabs_op = 0x05, 209 fmov_op = 0x06, fneg_op = 0x07, 210 froundl_op = 0x08, ftruncl_op = 0x09, 211 fceill_op = 0x0a, ffloorl_op = 0x0b, 212 fround_op = 0x0c, ftrunc_op = 0x0d, 213 fceil_op = 0x0e, ffloor_op = 0x0f, 214 fsel_op = 0x10, 215 fmovc_op = 0x11, fmovz_op = 0x12, 216 fmovn_op = 0x13, fseleqz_op = 0x14, 217 frecip_op = 0x15, frsqrt_op = 0x16, 218 fselnez_op = 0x17, fmaddf_op = 0x18, 219 fmsubf_op = 0x19, frint_op = 0x1a, 220 fclass_op = 0x1b, fmin_op = 0x1c, 221 fmina_op = 0x1d, fmax_op = 0x1e, 222 fmaxa_op = 0x1f, fcvts_op = 0x20, 223 fcvtd_op = 0x21, fcvte_op = 0x22, 224 fcvtw_op = 0x24, fcvtl_op = 0x25, 225 fcmp_op = 0x30 226 }; 227 228 /* 229 * func field of cop1x opcodes (MIPS IV). 230 */ 231 enum cop1x_func { 232 lwxc1_op = 0x00, ldxc1_op = 0x01, 233 swxc1_op = 0x08, sdxc1_op = 0x09, 234 pfetch_op = 0x0f, madd_s_op = 0x20, 235 madd_d_op = 0x21, madd_e_op = 0x22, 236 msub_s_op = 0x28, msub_d_op = 0x29, 237 msub_e_op = 0x2a, nmadd_s_op = 0x30, 238 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 239 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 240 nmsub_e_op = 0x3a 241 }; 242 243 /* 244 * func field for mad opcodes (MIPS IV). 245 */ 246 enum mad_func { 247 madd_fp_op = 0x08, msub_fp_op = 0x0a, 248 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 249 }; 250 251 /* 252 * func field for page table walker (Loongson-3). 253 */ 254 enum ptw_func { 255 lwdir_op = 0x00, 256 lwpte_op = 0x01, 257 lddir_op = 0x02, 258 ldpte_op = 0x03, 259 }; 260 261 /* 262 * func field for special3 lx opcodes (Cavium Octeon). 263 */ 264 enum lx_func { 265 lwx_op = 0x00, 266 lhx_op = 0x04, 267 lbux_op = 0x06, 268 ldx_op = 0x08, 269 lwux_op = 0x10, 270 lhux_op = 0x14, 271 lbx_op = 0x16, 272 }; 273 274 /* 275 * BSHFL opcodes 276 */ 277 enum bshfl_func { 278 wsbh_op = 0x2, 279 dshd_op = 0x5, 280 seb_op = 0x10, 281 seh_op = 0x18, 282 }; 283 284 /* 285 * MSA minor opcodes. 286 */ 287 enum msa_func { 288 msa_elm_op = 0x19, 289 }; 290 291 /* 292 * MSA ELM opcodes. 293 */ 294 enum msa_elm { 295 msa_ctc_op = 0x3e, 296 msa_cfc_op = 0x7e, 297 }; 298 299 /* 300 * func field for MSA MI10 format. 301 */ 302 enum msa_mi10_func { 303 msa_ld_op = 8, 304 msa_st_op = 9, 305 }; 306 307 /* 308 * MSA 2 bit format fields. 309 */ 310 enum msa_2b_fmt { 311 msa_fmt_b = 0, 312 msa_fmt_h = 1, 313 msa_fmt_w = 2, 314 msa_fmt_d = 3, 315 }; 316 317 /* 318 * (microMIPS) Major opcodes. 319 */ 320 enum mm_major_op { 321 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 322 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 323 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 324 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 325 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 326 mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op, 327 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 328 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 329 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 330 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 331 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 332 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 333 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 334 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 335 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 336 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 337 }; 338 339 /* 340 * (microMIPS) POOL32I minor opcodes. 341 */ 342 enum mm_32i_minor_op { 343 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 344 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 345 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 346 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 347 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 348 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 349 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 350 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 351 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 352 }; 353 354 /* 355 * (microMIPS) POOL32A minor opcodes. 356 */ 357 enum mm_32a_minor_op { 358 mm_sll32_op = 0x000, 359 mm_ins_op = 0x00c, 360 mm_sllv32_op = 0x010, 361 mm_ext_op = 0x02c, 362 mm_pool32axf_op = 0x03c, 363 mm_srl32_op = 0x040, 364 mm_sra_op = 0x080, 365 mm_srlv32_op = 0x090, 366 mm_rotr_op = 0x0c0, 367 mm_lwxs_op = 0x118, 368 mm_addu32_op = 0x150, 369 mm_subu32_op = 0x1d0, 370 mm_wsbh_op = 0x1ec, 371 mm_mul_op = 0x210, 372 mm_and_op = 0x250, 373 mm_or32_op = 0x290, 374 mm_xor32_op = 0x310, 375 mm_slt_op = 0x350, 376 mm_sltu_op = 0x390, 377 }; 378 379 /* 380 * (microMIPS) POOL32B functions. 381 */ 382 enum mm_32b_func { 383 mm_lwc2_func = 0x0, 384 mm_lwp_func = 0x1, 385 mm_ldc2_func = 0x2, 386 mm_ldp_func = 0x4, 387 mm_lwm32_func = 0x5, 388 mm_cache_func = 0x6, 389 mm_ldm_func = 0x7, 390 mm_swc2_func = 0x8, 391 mm_swp_func = 0x9, 392 mm_sdc2_func = 0xa, 393 mm_sdp_func = 0xc, 394 mm_swm32_func = 0xd, 395 mm_sdm_func = 0xf, 396 }; 397 398 /* 399 * (microMIPS) POOL32C functions. 400 */ 401 enum mm_32c_func { 402 mm_pref_func = 0x2, 403 mm_ll_func = 0x3, 404 mm_swr_func = 0x9, 405 mm_sc_func = 0xb, 406 mm_lwu_func = 0xe, 407 }; 408 409 /* 410 * (microMIPS) POOL32AXF minor opcodes. 411 */ 412 enum mm_32axf_minor_op { 413 mm_mfc0_op = 0x003, 414 mm_mtc0_op = 0x00b, 415 mm_tlbp_op = 0x00d, 416 mm_mfhi32_op = 0x035, 417 mm_jalr_op = 0x03c, 418 mm_tlbr_op = 0x04d, 419 mm_mflo32_op = 0x075, 420 mm_jalrhb_op = 0x07c, 421 mm_tlbwi_op = 0x08d, 422 mm_mthi32_op = 0x0b5, 423 mm_tlbwr_op = 0x0cd, 424 mm_mtlo32_op = 0x0f5, 425 mm_di_op = 0x11d, 426 mm_jalrs_op = 0x13c, 427 mm_jalrshb_op = 0x17c, 428 mm_sync_op = 0x1ad, 429 mm_syscall_op = 0x22d, 430 mm_wait_op = 0x24d, 431 mm_eret_op = 0x3cd, 432 mm_divu_op = 0x5dc, 433 }; 434 435 /* 436 * (microMIPS) POOL32F minor opcodes. 437 */ 438 enum mm_32f_minor_op { 439 mm_32f_00_op = 0x00, 440 mm_32f_01_op = 0x01, 441 mm_32f_02_op = 0x02, 442 mm_32f_10_op = 0x08, 443 mm_32f_11_op = 0x09, 444 mm_32f_12_op = 0x0a, 445 mm_32f_20_op = 0x10, 446 mm_32f_30_op = 0x18, 447 mm_32f_40_op = 0x20, 448 mm_32f_41_op = 0x21, 449 mm_32f_42_op = 0x22, 450 mm_32f_50_op = 0x28, 451 mm_32f_51_op = 0x29, 452 mm_32f_52_op = 0x2a, 453 mm_32f_60_op = 0x30, 454 mm_32f_70_op = 0x38, 455 mm_32f_73_op = 0x3b, 456 mm_32f_74_op = 0x3c, 457 }; 458 459 /* 460 * (microMIPS) POOL32F secondary minor opcodes. 461 */ 462 enum mm_32f_10_minor_op { 463 mm_lwxc1_op = 0x1, 464 mm_swxc1_op, 465 mm_ldxc1_op, 466 mm_sdxc1_op, 467 mm_luxc1_op, 468 mm_suxc1_op, 469 }; 470 471 enum mm_32f_func { 472 mm_lwxc1_func = 0x048, 473 mm_swxc1_func = 0x088, 474 mm_ldxc1_func = 0x0c8, 475 mm_sdxc1_func = 0x108, 476 }; 477 478 /* 479 * (microMIPS) POOL32F secondary minor opcodes. 480 */ 481 enum mm_32f_40_minor_op { 482 mm_fmovf_op, 483 mm_fmovt_op, 484 }; 485 486 /* 487 * (microMIPS) POOL32F secondary minor opcodes. 488 */ 489 enum mm_32f_60_minor_op { 490 mm_fadd_op, 491 mm_fsub_op, 492 mm_fmul_op, 493 mm_fdiv_op, 494 }; 495 496 /* 497 * (microMIPS) POOL32F secondary minor opcodes. 498 */ 499 enum mm_32f_70_minor_op { 500 mm_fmovn_op, 501 mm_fmovz_op, 502 }; 503 504 /* 505 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 506 */ 507 enum mm_32f_73_minor_op { 508 mm_fmov0_op = 0x01, 509 mm_fcvtl_op = 0x04, 510 mm_movf0_op = 0x05, 511 mm_frsqrt_op = 0x08, 512 mm_ffloorl_op = 0x0c, 513 mm_fabs0_op = 0x0d, 514 mm_fcvtw_op = 0x24, 515 mm_movt0_op = 0x25, 516 mm_fsqrt_op = 0x28, 517 mm_ffloorw_op = 0x2c, 518 mm_fneg0_op = 0x2d, 519 mm_cfc1_op = 0x40, 520 mm_frecip_op = 0x48, 521 mm_fceill_op = 0x4c, 522 mm_fcvtd0_op = 0x4d, 523 mm_ctc1_op = 0x60, 524 mm_fceilw_op = 0x6c, 525 mm_fcvts0_op = 0x6d, 526 mm_mfc1_op = 0x80, 527 mm_fmov1_op = 0x81, 528 mm_movf1_op = 0x85, 529 mm_ftruncl_op = 0x8c, 530 mm_fabs1_op = 0x8d, 531 mm_mtc1_op = 0xa0, 532 mm_movt1_op = 0xa5, 533 mm_ftruncw_op = 0xac, 534 mm_fneg1_op = 0xad, 535 mm_mfhc1_op = 0xc0, 536 mm_froundl_op = 0xcc, 537 mm_fcvtd1_op = 0xcd, 538 mm_mthc1_op = 0xe0, 539 mm_froundw_op = 0xec, 540 mm_fcvts1_op = 0xed, 541 }; 542 543 /* 544 * (microMIPS) POOL32S minor opcodes. 545 */ 546 enum mm_32s_minor_op { 547 mm_32s_elm_op = 0x16, 548 }; 549 550 /* 551 * (microMIPS) POOL16C minor opcodes. 552 */ 553 enum mm_16c_minor_op { 554 mm_lwm16_op = 0x04, 555 mm_swm16_op = 0x05, 556 mm_jr16_op = 0x0c, 557 mm_jrc_op = 0x0d, 558 mm_jalr16_op = 0x0e, 559 mm_jalrs16_op = 0x0f, 560 mm_jraddiusp_op = 0x18, 561 }; 562 563 /* 564 * (microMIPS) POOL16D minor opcodes. 565 */ 566 enum mm_16d_minor_op { 567 mm_addius5_func, 568 mm_addiusp_func, 569 }; 570 571 /* 572 * (MIPS16e) opcodes. 573 */ 574 enum MIPS16e_ops { 575 MIPS16e_jal_op = 003, 576 MIPS16e_ld_op = 007, 577 MIPS16e_i8_op = 014, 578 MIPS16e_sd_op = 017, 579 MIPS16e_lb_op = 020, 580 MIPS16e_lh_op = 021, 581 MIPS16e_lwsp_op = 022, 582 MIPS16e_lw_op = 023, 583 MIPS16e_lbu_op = 024, 584 MIPS16e_lhu_op = 025, 585 MIPS16e_lwpc_op = 026, 586 MIPS16e_lwu_op = 027, 587 MIPS16e_sb_op = 030, 588 MIPS16e_sh_op = 031, 589 MIPS16e_swsp_op = 032, 590 MIPS16e_sw_op = 033, 591 MIPS16e_rr_op = 035, 592 MIPS16e_extend_op = 036, 593 MIPS16e_i64_op = 037, 594 }; 595 596 enum MIPS16e_i64_func { 597 MIPS16e_ldsp_func, 598 MIPS16e_sdsp_func, 599 MIPS16e_sdrasp_func, 600 MIPS16e_dadjsp_func, 601 MIPS16e_ldpc_func, 602 }; 603 604 enum MIPS16e_rr_func { 605 MIPS16e_jr_func, 606 }; 607 608 enum MIPS6e_i8_func { 609 MIPS16e_swrasp_func = 02, 610 }; 611 612 /* 613 * (microMIPS) NOP instruction. 614 */ 615 #define MM_NOP16 0x0c00 616 617 struct j_format { 618 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 619 __BITFIELD_FIELD(unsigned int target : 26, 620 ;)) 621 }; 622 623 struct i_format { /* signed immediate format */ 624 __BITFIELD_FIELD(unsigned int opcode : 6, 625 __BITFIELD_FIELD(unsigned int rs : 5, 626 __BITFIELD_FIELD(unsigned int rt : 5, 627 __BITFIELD_FIELD(signed int simmediate : 16, 628 ;)))) 629 }; 630 631 struct u_format { /* unsigned immediate format */ 632 __BITFIELD_FIELD(unsigned int opcode : 6, 633 __BITFIELD_FIELD(unsigned int rs : 5, 634 __BITFIELD_FIELD(unsigned int rt : 5, 635 __BITFIELD_FIELD(unsigned int uimmediate : 16, 636 ;)))) 637 }; 638 639 struct c_format { /* Cache (>= R6000) format */ 640 __BITFIELD_FIELD(unsigned int opcode : 6, 641 __BITFIELD_FIELD(unsigned int rs : 5, 642 __BITFIELD_FIELD(unsigned int c_op : 3, 643 __BITFIELD_FIELD(unsigned int cache : 2, 644 __BITFIELD_FIELD(unsigned int simmediate : 16, 645 ;))))) 646 }; 647 648 struct r_format { /* Register format */ 649 __BITFIELD_FIELD(unsigned int opcode : 6, 650 __BITFIELD_FIELD(unsigned int rs : 5, 651 __BITFIELD_FIELD(unsigned int rt : 5, 652 __BITFIELD_FIELD(unsigned int rd : 5, 653 __BITFIELD_FIELD(unsigned int re : 5, 654 __BITFIELD_FIELD(unsigned int func : 6, 655 ;)))))) 656 }; 657 658 struct c0r_format { /* C0 register format */ 659 __BITFIELD_FIELD(unsigned int opcode : 6, 660 __BITFIELD_FIELD(unsigned int rs : 5, 661 __BITFIELD_FIELD(unsigned int rt : 5, 662 __BITFIELD_FIELD(unsigned int rd : 5, 663 __BITFIELD_FIELD(unsigned int z: 8, 664 __BITFIELD_FIELD(unsigned int sel : 3, 665 ;)))))) 666 }; 667 668 struct mfmc0_format { /* MFMC0 register format */ 669 __BITFIELD_FIELD(unsigned int opcode : 6, 670 __BITFIELD_FIELD(unsigned int rs : 5, 671 __BITFIELD_FIELD(unsigned int rt : 5, 672 __BITFIELD_FIELD(unsigned int rd : 5, 673 __BITFIELD_FIELD(unsigned int re : 5, 674 __BITFIELD_FIELD(unsigned int sc : 1, 675 __BITFIELD_FIELD(unsigned int : 2, 676 __BITFIELD_FIELD(unsigned int sel : 3, 677 ;)))))))) 678 }; 679 680 struct co_format { /* C0 CO format */ 681 __BITFIELD_FIELD(unsigned int opcode : 6, 682 __BITFIELD_FIELD(unsigned int co : 1, 683 __BITFIELD_FIELD(unsigned int code : 19, 684 __BITFIELD_FIELD(unsigned int func : 6, 685 ;)))) 686 }; 687 688 struct p_format { /* Performance counter format (R10000) */ 689 __BITFIELD_FIELD(unsigned int opcode : 6, 690 __BITFIELD_FIELD(unsigned int rs : 5, 691 __BITFIELD_FIELD(unsigned int rt : 5, 692 __BITFIELD_FIELD(unsigned int rd : 5, 693 __BITFIELD_FIELD(unsigned int re : 5, 694 __BITFIELD_FIELD(unsigned int func : 6, 695 ;)))))) 696 }; 697 698 struct f_format { /* FPU register format */ 699 __BITFIELD_FIELD(unsigned int opcode : 6, 700 __BITFIELD_FIELD(unsigned int : 1, 701 __BITFIELD_FIELD(unsigned int fmt : 4, 702 __BITFIELD_FIELD(unsigned int rt : 5, 703 __BITFIELD_FIELD(unsigned int rd : 5, 704 __BITFIELD_FIELD(unsigned int re : 5, 705 __BITFIELD_FIELD(unsigned int func : 6, 706 ;))))))) 707 }; 708 709 struct ma_format { /* FPU multiply and add format (MIPS IV) */ 710 __BITFIELD_FIELD(unsigned int opcode : 6, 711 __BITFIELD_FIELD(unsigned int fr : 5, 712 __BITFIELD_FIELD(unsigned int ft : 5, 713 __BITFIELD_FIELD(unsigned int fs : 5, 714 __BITFIELD_FIELD(unsigned int fd : 5, 715 __BITFIELD_FIELD(unsigned int func : 4, 716 __BITFIELD_FIELD(unsigned int fmt : 2, 717 ;))))))) 718 }; 719 720 struct b_format { /* BREAK and SYSCALL */ 721 __BITFIELD_FIELD(unsigned int opcode : 6, 722 __BITFIELD_FIELD(unsigned int code : 20, 723 __BITFIELD_FIELD(unsigned int func : 6, 724 ;))) 725 }; 726 727 struct ps_format { /* MIPS-3D / paired single format */ 728 __BITFIELD_FIELD(unsigned int opcode : 6, 729 __BITFIELD_FIELD(unsigned int rs : 5, 730 __BITFIELD_FIELD(unsigned int ft : 5, 731 __BITFIELD_FIELD(unsigned int fs : 5, 732 __BITFIELD_FIELD(unsigned int fd : 5, 733 __BITFIELD_FIELD(unsigned int func : 6, 734 ;)))))) 735 }; 736 737 struct v_format { /* MDMX vector format */ 738 __BITFIELD_FIELD(unsigned int opcode : 6, 739 __BITFIELD_FIELD(unsigned int sel : 4, 740 __BITFIELD_FIELD(unsigned int fmt : 1, 741 __BITFIELD_FIELD(unsigned int vt : 5, 742 __BITFIELD_FIELD(unsigned int vs : 5, 743 __BITFIELD_FIELD(unsigned int vd : 5, 744 __BITFIELD_FIELD(unsigned int func : 6, 745 ;))))))) 746 }; 747 748 struct msa_mi10_format { /* MSA MI10 */ 749 __BITFIELD_FIELD(unsigned int opcode : 6, 750 __BITFIELD_FIELD(signed int s10 : 10, 751 __BITFIELD_FIELD(unsigned int rs : 5, 752 __BITFIELD_FIELD(unsigned int wd : 5, 753 __BITFIELD_FIELD(unsigned int func : 4, 754 __BITFIELD_FIELD(unsigned int df : 2, 755 ;)))))) 756 }; 757 758 struct spec3_format { /* SPEC3 */ 759 __BITFIELD_FIELD(unsigned int opcode:6, 760 __BITFIELD_FIELD(unsigned int rs:5, 761 __BITFIELD_FIELD(unsigned int rt:5, 762 __BITFIELD_FIELD(signed int simmediate:9, 763 __BITFIELD_FIELD(unsigned int func:7, 764 ;))))) 765 }; 766 767 /* 768 * microMIPS instruction formats (32-bit length) 769 * 770 * NOTE: 771 * Parenthesis denote whether the format is a microMIPS instruction or 772 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 773 */ 774 struct fb_format { /* FPU branch format (MIPS32) */ 775 __BITFIELD_FIELD(unsigned int opcode : 6, 776 __BITFIELD_FIELD(unsigned int bc : 5, 777 __BITFIELD_FIELD(unsigned int cc : 3, 778 __BITFIELD_FIELD(unsigned int flag : 2, 779 __BITFIELD_FIELD(signed int simmediate : 16, 780 ;))))) 781 }; 782 783 struct fp0_format { /* FPU multiply and add format (MIPS32) */ 784 __BITFIELD_FIELD(unsigned int opcode : 6, 785 __BITFIELD_FIELD(unsigned int fmt : 5, 786 __BITFIELD_FIELD(unsigned int ft : 5, 787 __BITFIELD_FIELD(unsigned int fs : 5, 788 __BITFIELD_FIELD(unsigned int fd : 5, 789 __BITFIELD_FIELD(unsigned int func : 6, 790 ;)))))) 791 }; 792 793 struct mm_fp0_format { /* FPU multiply and add format (microMIPS) */ 794 __BITFIELD_FIELD(unsigned int opcode : 6, 795 __BITFIELD_FIELD(unsigned int ft : 5, 796 __BITFIELD_FIELD(unsigned int fs : 5, 797 __BITFIELD_FIELD(unsigned int fd : 5, 798 __BITFIELD_FIELD(unsigned int fmt : 3, 799 __BITFIELD_FIELD(unsigned int op : 2, 800 __BITFIELD_FIELD(unsigned int func : 6, 801 ;))))))) 802 }; 803 804 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 805 __BITFIELD_FIELD(unsigned int opcode : 6, 806 __BITFIELD_FIELD(unsigned int op : 5, 807 __BITFIELD_FIELD(unsigned int rt : 5, 808 __BITFIELD_FIELD(unsigned int fs : 5, 809 __BITFIELD_FIELD(unsigned int fd : 5, 810 __BITFIELD_FIELD(unsigned int func : 6, 811 ;)))))) 812 }; 813 814 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 815 __BITFIELD_FIELD(unsigned int opcode : 6, 816 __BITFIELD_FIELD(unsigned int rt : 5, 817 __BITFIELD_FIELD(unsigned int fs : 5, 818 __BITFIELD_FIELD(unsigned int fmt : 2, 819 __BITFIELD_FIELD(unsigned int op : 8, 820 __BITFIELD_FIELD(unsigned int func : 6, 821 ;)))))) 822 }; 823 824 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 825 __BITFIELD_FIELD(unsigned int opcode : 6, 826 __BITFIELD_FIELD(unsigned int fd : 5, 827 __BITFIELD_FIELD(unsigned int fs : 5, 828 __BITFIELD_FIELD(unsigned int cc : 3, 829 __BITFIELD_FIELD(unsigned int zero : 2, 830 __BITFIELD_FIELD(unsigned int fmt : 2, 831 __BITFIELD_FIELD(unsigned int op : 3, 832 __BITFIELD_FIELD(unsigned int func : 6, 833 ;)))))))) 834 }; 835 836 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 837 __BITFIELD_FIELD(unsigned int opcode : 6, 838 __BITFIELD_FIELD(unsigned int rt : 5, 839 __BITFIELD_FIELD(unsigned int fs : 5, 840 __BITFIELD_FIELD(unsigned int fmt : 3, 841 __BITFIELD_FIELD(unsigned int op : 7, 842 __BITFIELD_FIELD(unsigned int func : 6, 843 ;)))))) 844 }; 845 846 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 847 __BITFIELD_FIELD(unsigned int opcode : 6, 848 __BITFIELD_FIELD(unsigned int rt : 5, 849 __BITFIELD_FIELD(unsigned int fs : 5, 850 __BITFIELD_FIELD(unsigned int cc : 3, 851 __BITFIELD_FIELD(unsigned int fmt : 3, 852 __BITFIELD_FIELD(unsigned int cond : 4, 853 __BITFIELD_FIELD(unsigned int func : 6, 854 ;))))))) 855 }; 856 857 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 858 __BITFIELD_FIELD(unsigned int opcode : 6, 859 __BITFIELD_FIELD(unsigned int index : 5, 860 __BITFIELD_FIELD(unsigned int base : 5, 861 __BITFIELD_FIELD(unsigned int fd : 5, 862 __BITFIELD_FIELD(unsigned int op : 5, 863 __BITFIELD_FIELD(unsigned int func : 6, 864 ;)))))) 865 }; 866 867 struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 868 __BITFIELD_FIELD(unsigned int opcode : 6, 869 __BITFIELD_FIELD(unsigned int fr : 5, 870 __BITFIELD_FIELD(unsigned int ft : 5, 871 __BITFIELD_FIELD(unsigned int fs : 5, 872 __BITFIELD_FIELD(unsigned int fd : 5, 873 __BITFIELD_FIELD(unsigned int func : 6, 874 ;)))))) 875 }; 876 877 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 878 __BITFIELD_FIELD(unsigned int opcode : 6, 879 __BITFIELD_FIELD(unsigned int ft : 5, 880 __BITFIELD_FIELD(unsigned int fs : 5, 881 __BITFIELD_FIELD(unsigned int fd : 5, 882 __BITFIELD_FIELD(unsigned int fr : 5, 883 __BITFIELD_FIELD(unsigned int func : 6, 884 ;)))))) 885 }; 886 887 struct mm_i_format { /* Immediate format (microMIPS) */ 888 __BITFIELD_FIELD(unsigned int opcode : 6, 889 __BITFIELD_FIELD(unsigned int rt : 5, 890 __BITFIELD_FIELD(unsigned int rs : 5, 891 __BITFIELD_FIELD(signed int simmediate : 16, 892 ;)))) 893 }; 894 895 struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 896 __BITFIELD_FIELD(unsigned int opcode : 6, 897 __BITFIELD_FIELD(unsigned int rd : 5, 898 __BITFIELD_FIELD(unsigned int base : 5, 899 __BITFIELD_FIELD(unsigned int func : 4, 900 __BITFIELD_FIELD(signed int simmediate : 12, 901 ;))))) 902 }; 903 904 struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 905 __BITFIELD_FIELD(unsigned int opcode : 6, 906 __BITFIELD_FIELD(unsigned int index : 5, 907 __BITFIELD_FIELD(unsigned int base : 5, 908 __BITFIELD_FIELD(unsigned int rd : 5, 909 __BITFIELD_FIELD(unsigned int func : 11, 910 ;))))) 911 }; 912 913 struct mm_a_format { /* ADDIUPC format (microMIPS) */ 914 __BITFIELD_FIELD(unsigned int opcode : 6, 915 __BITFIELD_FIELD(unsigned int rs : 3, 916 __BITFIELD_FIELD(signed int simmediate : 23, 917 ;))) 918 }; 919 920 /* 921 * microMIPS instruction formats (16-bit length) 922 */ 923 struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 924 __BITFIELD_FIELD(unsigned int opcode : 6, 925 __BITFIELD_FIELD(signed int simmediate : 10, 926 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 927 ;))) 928 }; 929 930 struct mm_b1_format { /* Conditional branch format (microMIPS) */ 931 __BITFIELD_FIELD(unsigned int opcode : 6, 932 __BITFIELD_FIELD(unsigned int rs : 3, 933 __BITFIELD_FIELD(signed int simmediate : 7, 934 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 935 ;)))) 936 }; 937 938 struct mm16_m_format { /* Multi-word load/store format */ 939 __BITFIELD_FIELD(unsigned int opcode : 6, 940 __BITFIELD_FIELD(unsigned int func : 4, 941 __BITFIELD_FIELD(unsigned int rlist : 2, 942 __BITFIELD_FIELD(unsigned int imm : 4, 943 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 944 ;))))) 945 }; 946 947 struct mm16_rb_format { /* Signed immediate format */ 948 __BITFIELD_FIELD(unsigned int opcode : 6, 949 __BITFIELD_FIELD(unsigned int rt : 3, 950 __BITFIELD_FIELD(unsigned int base : 3, 951 __BITFIELD_FIELD(signed int simmediate : 4, 952 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 953 ;))))) 954 }; 955 956 struct mm16_r3_format { /* Load from global pointer format */ 957 __BITFIELD_FIELD(unsigned int opcode : 6, 958 __BITFIELD_FIELD(unsigned int rt : 3, 959 __BITFIELD_FIELD(signed int simmediate : 7, 960 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 961 ;)))) 962 }; 963 964 struct mm16_r5_format { /* Load/store from stack pointer format */ 965 __BITFIELD_FIELD(unsigned int opcode : 6, 966 __BITFIELD_FIELD(unsigned int rt : 5, 967 __BITFIELD_FIELD(signed int simmediate : 5, 968 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 969 ;)))) 970 }; 971 972 /* 973 * MIPS16e instruction formats (16-bit length) 974 */ 975 struct m16e_rr { 976 __BITFIELD_FIELD(unsigned int opcode : 5, 977 __BITFIELD_FIELD(unsigned int rx : 3, 978 __BITFIELD_FIELD(unsigned int nd : 1, 979 __BITFIELD_FIELD(unsigned int l : 1, 980 __BITFIELD_FIELD(unsigned int ra : 1, 981 __BITFIELD_FIELD(unsigned int func : 5, 982 ;)))))) 983 }; 984 985 struct m16e_jal { 986 __BITFIELD_FIELD(unsigned int opcode : 5, 987 __BITFIELD_FIELD(unsigned int x : 1, 988 __BITFIELD_FIELD(unsigned int imm20_16 : 5, 989 __BITFIELD_FIELD(signed int imm25_21 : 5, 990 ;)))) 991 }; 992 993 struct m16e_i64 { 994 __BITFIELD_FIELD(unsigned int opcode : 5, 995 __BITFIELD_FIELD(unsigned int func : 3, 996 __BITFIELD_FIELD(unsigned int imm : 8, 997 ;))) 998 }; 999 1000 struct m16e_ri64 { 1001 __BITFIELD_FIELD(unsigned int opcode : 5, 1002 __BITFIELD_FIELD(unsigned int func : 3, 1003 __BITFIELD_FIELD(unsigned int ry : 3, 1004 __BITFIELD_FIELD(unsigned int imm : 5, 1005 ;)))) 1006 }; 1007 1008 struct m16e_ri { 1009 __BITFIELD_FIELD(unsigned int opcode : 5, 1010 __BITFIELD_FIELD(unsigned int rx : 3, 1011 __BITFIELD_FIELD(unsigned int imm : 8, 1012 ;))) 1013 }; 1014 1015 struct m16e_rri { 1016 __BITFIELD_FIELD(unsigned int opcode : 5, 1017 __BITFIELD_FIELD(unsigned int rx : 3, 1018 __BITFIELD_FIELD(unsigned int ry : 3, 1019 __BITFIELD_FIELD(unsigned int imm : 5, 1020 ;)))) 1021 }; 1022 1023 struct m16e_i8 { 1024 __BITFIELD_FIELD(unsigned int opcode : 5, 1025 __BITFIELD_FIELD(unsigned int func : 3, 1026 __BITFIELD_FIELD(unsigned int imm : 8, 1027 ;))) 1028 }; 1029 1030 union mips_instruction { 1031 unsigned int word; 1032 unsigned short halfword[2]; 1033 unsigned char byte[4]; 1034 struct j_format j_format; 1035 struct i_format i_format; 1036 struct u_format u_format; 1037 struct c_format c_format; 1038 struct r_format r_format; 1039 struct c0r_format c0r_format; 1040 struct mfmc0_format mfmc0_format; 1041 struct co_format co_format; 1042 struct p_format p_format; 1043 struct f_format f_format; 1044 struct ma_format ma_format; 1045 struct msa_mi10_format msa_mi10_format; 1046 struct b_format b_format; 1047 struct ps_format ps_format; 1048 struct v_format v_format; 1049 struct spec3_format spec3_format; 1050 struct fb_format fb_format; 1051 struct fp0_format fp0_format; 1052 struct mm_fp0_format mm_fp0_format; 1053 struct fp1_format fp1_format; 1054 struct mm_fp1_format mm_fp1_format; 1055 struct mm_fp2_format mm_fp2_format; 1056 struct mm_fp3_format mm_fp3_format; 1057 struct mm_fp4_format mm_fp4_format; 1058 struct mm_fp5_format mm_fp5_format; 1059 struct fp6_format fp6_format; 1060 struct mm_fp6_format mm_fp6_format; 1061 struct mm_i_format mm_i_format; 1062 struct mm_m_format mm_m_format; 1063 struct mm_x_format mm_x_format; 1064 struct mm_a_format mm_a_format; 1065 struct mm_b0_format mm_b0_format; 1066 struct mm_b1_format mm_b1_format; 1067 struct mm16_m_format mm16_m_format ; 1068 struct mm16_rb_format mm16_rb_format; 1069 struct mm16_r3_format mm16_r3_format; 1070 struct mm16_r5_format mm16_r5_format; 1071 }; 1072 1073 union mips16e_instruction { 1074 unsigned int full : 16; 1075 struct m16e_rr rr; 1076 struct m16e_jal jal; 1077 struct m16e_i64 i64; 1078 struct m16e_ri64 ri64; 1079 struct m16e_ri ri; 1080 struct m16e_rri rri; 1081 struct m16e_i8 i8; 1082 }; 1083 1084 #endif /* _UAPI_ASM_INST_H */ 1085