Home
last modified time | relevance | path

Searched refs:bclr (Results 1 – 25 of 29) sorted by relevance

12

/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-ext.txt4 # CHECK: bclr 12, 2
8 # CHECK: bclr 12, 6
12 # CHECK: bclr 12, 10
16 # CHECK: bclr 12, 14
20 # CHECK: bclr 12, 18
24 # CHECK: bclr 12, 22
28 # CHECK: bclr 12, 26
32 # CHECK: bclr 12, 30
35 # CHECK: bclr 12, 0
38 # CHECK: bclr 12, 1
[all …]
Dppc64le-encoding.txt19 # CHECK: bclr 4, 10, 3
22 # CHECK: bclr 4, 10
Dppc64-encoding.txt19 # CHECK: bclr 4, 10, 3
22 # CHECK: bclr 4, 10
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-ext.s32 # CHECK-BE: bclr 12, 0 # encoding: [0x4d,0x80,0x00,0x20]
33 # CHECK-LE: bclr 12, 0 # encoding: [0x20,0x00,0x80,0x4d]
35 # CHECK-BE: bclr 12, 1 # encoding: [0x4d,0x81,0x00,0x20]
36 # CHECK-LE: bclr 12, 1 # encoding: [0x20,0x00,0x81,0x4d]
38 # CHECK-BE: bclr 12, 2 # encoding: [0x4d,0x82,0x00,0x20]
39 # CHECK-LE: bclr 12, 2 # encoding: [0x20,0x00,0x82,0x4d]
41 # CHECK-BE: bclr 12, 3 # encoding: [0x4d,0x83,0x00,0x20]
42 # CHECK-LE: bclr 12, 3 # encoding: [0x20,0x00,0x83,0x4d]
44 # CHECK-BE: bclr 12, 3 # encoding: [0x4d,0x83,0x00,0x20]
45 # CHECK-LE: bclr 12, 3 # encoding: [0x20,0x00,0x83,0x4d]
[all …]
Dppc64-encoding.s51 # CHECK-BE: bclr 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x20]
52 # CHECK-LE: bclr 4, 10, 3 # encoding: [0x20,0x18,0x8a,0x4c]
53 bclr 4, 10, 3
54 # CHECK-BE: bclr 4, 10 # encoding: [0x4c,0x8a,0x00,0x20]
55 # CHECK-LE: bclr 4, 10 # encoding: [0x20,0x00,0x8a,0x4c]
56 bclr 4, 10
/external/llvm/test/CodeGen/PowerPC/
Dandc.ll11 ; CHECK-NEXT: bclr 12, 2, 0
27 ; CHECK-NEXT: bclr 12, 2, 0
Dbdzlr.ll61 ; CHECK-CRB: bclr 12,
62 ; CHECK-CRB: bclr 12,
Dearly-ret2.ll23 ; CHECK-CRB: bclr 12,
Dselect-i1-vs-i1.ll717 ; FIXME: This test (and the other v4f32 tests) should use the same bclr
955 ; CHECK: bclr 12, [[REG1]], 0
972 ; CHECK: bclr 12, [[REG1]], 0
989 ; CHECK: bclr 12, [[REG1]], 0
1006 ; CHECK: bclr 12, [[REG1]], 0
1023 ; CHECK: bclr 12, [[REG1]], 0
1040 ; CHECK: bclr 12, [[REG1]], 0
1057 ; CHECK: bclr 12, [[REG1]], 0
1074 ; CHECK: bclr 12, [[REG1]], 0
1091 ; CHECK: bclr 12, [[REG1]], 0
[all …]
Dcrbits.ll168 ; CHECK: bclr 12, 1, 0
/external/llvm/test/CodeGen/Mips/msa/
D3r-b.ll15 %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1)
20 declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind
25 ; CHECK: bclr.b
37 %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1)
42 declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind
47 ; CHECK: bclr.h
59 %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1)
64 declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind
69 ; CHECK: bclr.w
81 %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1)
[all …]
Dbitwise.ll1258 ; CHECK-DAG: bclr.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1276 ; CHECK-DAG: bclr.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1294 ; CHECK-DAG: bclr.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
1312 ; CHECK-DAG: bclr.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
/external/v8/src/ppc/
Dassembler-ppc.h570 void bclr(BOfield bo, int condition_bit, LKBit lk);
663 void bclr(Condition cond, CRegister cr = cr7, LKBit lk = LeaveLK) {
671 bclr(BT, encode_crbit(cr, CR_EQ), lk);
674 bclr(BF, encode_crbit(cr, CR_EQ), lk);
677 bclr(BT, encode_crbit(cr, CR_GT), lk);
680 bclr(BF, encode_crbit(cr, CR_GT), lk);
683 bclr(BT, encode_crbit(cr, CR_LT), lk);
686 bclr(BF, encode_crbit(cr, CR_LT), lk);
689 bclr(BT, encode_crbit(cr, CR_FU), lk);
692 bclr(BF, encode_crbit(cr, CR_FU), lk);
[all …]
Dassembler-ppc.cc724 void Assembler::bclr(BOfield bo, int condition_bit, LKBit lk) { in bclr() function in v8::internal::Assembler
735 void Assembler::blr() { bclr(BA, 0, LeaveLK); } in blr()
Dmacro-assembler-ppc.h141 void Ret(Condition cond, CRegister cr = cr7) { bclr(cond, cr); }
Dconstants-ppc.h2114 V(bclr, BCLRX, 0x4C000020) \
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s47 # CHECK: bclr.b $w2, $w15, $w29 # encoding: [0x79,0x9d,0x78,0x8d]
48 # CHECK: bclr.h $w16, $w21, $w28 # encoding: [0x79,0xbc,0xac,0x0d]
49 # CHECK: bclr.w $w19, $w2, $w9 # encoding: [0x79,0xc9,0x14,0xcd]
50 # CHECK: bclr.d $w27, $w31, $w4 # encoding: [0x79,0xe4,0xfe,0xcd]
290 bclr.b $w2, $w15, $w29
291 bclr.h $w16, $w21, $w28
292 bclr.w $w19, $w2, $w9
293 bclr.d $w27, $w31, $w4
/external/llvm/test/MC/Sparc/
Dsparc-synthetic-instructions.s94 bclr %g1, %g2
96 bclr 4, %g2
/external/boringssl/linux-ppc64le/crypto/aes/
Daesp8-ppc.S471 bclr 14,0
1206 bclr 14,0
1835 bclr 14,0
2046 bclr 14,0
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt47 0x79 0x9d 0x78 0x8d # CHECK: bclr.b $w2, $w15, $w29
48 0x79 0xbc 0xac 0x0d # CHECK: bclr.h $w16, $w21, $w28
49 0x79 0xc9 0x14 0xcd # CHECK: bclr.w $w19, $w2, $w9
50 0x79 0xe4 0xfe 0xcd # CHECK: bclr.d $w27, $w31, $w4
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td418 // bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
419 def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
420 def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCSchedule.td133 // bclr BrB
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1599 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
1600 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
1601 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
1602 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td1210 "bclr 12, $bi, 0", IIC_BrB, []>;
1212 "bclr 4, $bi, 0", IIC_BrB, []>;
4060 "bclr $bo, $bi, $bh", IIC_BrB, []>;
4074 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td1688 "bclr\t$s",

12