1// RUN: not llvm-mc -triple=thumbv8m.base -show-encoding < %s 2>%t \ 2// RUN: | FileCheck --check-prefix=CHECK-BASELINE --check-prefix=CHECK %s 3// RUN: FileCheck --check-prefix=UNDEF-BASELINE --check-prefix=UNDEF < %t %s 4// RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \ 5// RUN: | FileCheck --check-prefix=CHECK-MAINLINE --check-prefix=CHECK %s 6// RUN: FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s 7// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+dsp,+t2xtpk -show-encoding < %s 2>%t \ 8// RUN: | FileCheck --check-prefix=CHECK-MAINLINE_DSP --check-prefix=CHECK %s 9// RUN: FileCheck --check-prefix=UNDEF-MAINLINE_DSP --check-prefix=UNDEF < %t %s 10 11// Simple check that baseline is v6M and mainline is v7M 12// UNDEF-BASELINE: error: instruction requires: thumb2 13// UNDEF-MAINLINE-NOT: error: instruction requires: 14// UNDEF-MAINLINE_DSP-NOT: error: instruction requires: 15mov.w r0, r0 16 17// Check that .arm is invalid 18// UNDEF: target does not support ARM mode 19.arm 20 21// And only +dsp,+t2xtpk has DSP and t2xtpk instructions 22// UNDEF-BASELINE: error: instruction requires: arm-mode 23// UNDEF-MAINLINE: error: instruction requires: arm-mode 24// UNDEF-MAINLINE_DSP-NOT: error: instruction requires: 25qadd16 r0, r0, r0 26// UNDEF-BASELINE: error: instruction requires: arm-mode 27// UNDEF-MAINLINE: error: instruction requires: arm-mode 28// UNDEF-MAINLINE_DSP-NOT: error: instruction requires: 29uxtab16 r0, r1, r2 30 31// Instruction availibility checks 32 33// 'Barrier instructions' 34 35// CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f] 36isb sy 37 38// 'Code optimization' 39 40// CHECK: cbz r3, .Ltmp0 @ encoding: [0x03'A',0xb1'A'] 41// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb 42cbz r3, 1f 43 44// CHECK: cbnz r3, .Ltmp0 @ encoding: [0x03'A',0xb9'A'] 45// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb 46cbnz r3, 1f 47 48// CHECK: b.w .Ltmp0 @ encoding: [A,0xf0'A',A,0x90'A'] 49// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_t2_uncondbranch 50b.w 1f 51 52// CHECK: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1] 53sdiv r1, r2, r3 54 55// CHECK: udiv r1, r2, r3 @ encoding: [0xb2,0xfb,0xf3,0xf1] 56udiv r1, r2, r3 57 58// 'Exclusives from ARMv7-M' 59 60// CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f] 61clrex 62 63// CHECK: ldrex r1, [r2, #4] @ encoding: [0x52,0xe8,0x01,0x1f] 64ldrex r1, [r2, #4] 65 66// CHECK: ldrexb r1, [r2] @ encoding: [0xd2,0xe8,0x4f,0x1f] 67ldrexb r1, [r2] 68 69// CHECK: ldrexh r1, [r2] @ encoding: [0xd2,0xe8,0x5f,0x1f] 70ldrexh r1, [r2] 71 72// UNDEF-BASELINE: error: instruction requires: !armv*m thumb2 73// UNDEF-MAINLINE: error: instruction requires: !armv*m 74ldrexd r0, r1, [r2] 75 76// CHECK: strex r1, r2, [r3, #4] @ encoding: [0x43,0xe8,0x01,0x21] 77strex r1, r2, [r3, #4] 78 79// CHECK: strexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0x41,0x2f] 80strexb r1, r2, [r3] 81 82// CHECK: strexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0x51,0x2f] 83strexh r1, r2, [r3] 84 85// UNDEF-BASELINE: error: instruction requires: !armv*m thumb2 86// UNDEF-MAINLINE: error: instruction requires: !armv*m 87strexd r0, r1, r2, [r3] 88 89// 'XO generation' 90 91// CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71] 92movw r1, #0xffff 93 94// CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71] 95movt r1, #0xffff 96 97// 'Acquire/Release from ARMv8-A' 98 99// CHECK: lda r1, [r2] @ encoding: [0xd2,0xe8,0xaf,0x1f] 100lda r1, [r2] 101 102// CHECK: ldab r1, [r2] @ encoding: [0xd2,0xe8,0x8f,0x1f] 103ldab r1, [r2] 104 105// CHECK: ldah r1, [r2] @ encoding: [0xd2,0xe8,0x9f,0x1f] 106ldah r1, [r2] 107 108// CHECK: stl r1, [r3] @ encoding: [0xc3,0xe8,0xaf,0x1f] 109stl r1, [r3] 110 111// CHECK: stlb r1, [r3] @ encoding: [0xc3,0xe8,0x8f,0x1f] 112stlb r1, [r3] 113 114// CHECK: stlh r1, [r3] @ encoding: [0xc3,0xe8,0x9f,0x1f] 115stlh r1, [r3] 116 117// CHECK: ldaex r1, [r2] @ encoding: [0xd2,0xe8,0xef,0x1f] 118ldaex r1, [r2] 119 120// CHECK: ldaexb r1, [r2] @ encoding: [0xd2,0xe8,0xcf,0x1f] 121ldaexb r1, [r2] 122 123// CHECK: ldaexh r1, [r2] @ encoding: [0xd2,0xe8,0xdf,0x1f] 124ldaexh r1, [r2] 125 126// UNDEF: error: instruction requires: !armv*m 127ldaexd r0, r1, [r2] 128 129// CHECK: stlex r1, r2, [r3] @ encoding: [0xc3,0xe8,0xe1,0x2f] 130stlex r1, r2, [r3] 131 132// CHECK: stlexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0xc1,0x2f] 133stlexb r1, r2, [r3] 134 135// CHECK: stlexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0xd1,0x2f] 136stlexh r1, r2, [r3] 137 138// UNDEF: error: instruction requires: !armv*m 139stlexd r0, r1, r2, [r2] 140 141// ARMv8-M Security Extensions 142 143// CHECK: sg @ encoding: [0x7f,0xe9,0x7f,0xe9] 144sg 145 146// CHECK: bxns r0 @ encoding: [0x04,0x47] 147bxns r0 148 149// UNDEF-BASELINE: error: invalid operand for instruction 150// UNDEF-BASELINE: error: conditional execution not supported in Thumb1 151// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf] 152// CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47] 153it eq 154bxnseq r1 155 156// CHECK: bxns lr @ encoding: [0x74,0x47] 157bxns lr 158 159// CHECK: blxns r0 @ encoding: [0x84,0x47] 160blxns r0 161 162// UNDEF-BASELINE: error: invalid operand for instruction 163// UNDEF-BASELINE: error: conditional execution not supported in Thumb1 164// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf] 165// CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47] 166it eq 167blxnseq r1 168 169// CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0] 170tt r0, r1 171 172// CHECK: tt r0, sp @ encoding: [0x4d,0xe8,0x00,0xf0] 173tt r0, sp 174 175// CHECK: tta r0, r1 @ encoding: [0x41,0xe8,0x80,0xf0] 176tta r0, r1 177 178// CHECK: ttt r0, r1 @ encoding: [0x41,0xe8,0x40,0xf0] 179ttt r0, r1 180 181// CHECK: ttat r0, r1 @ encoding: [0x41,0xe8,0xc0,0xf0] 182ttat r0, r1 183 184// 'Lazy Load/Store Multiple' 185 186// UNDEF-BASELINE: error: instruction requires: armv8m.main 187// CHECK-MAINLINE: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a] 188// CHECK-MAINLINE_DSP: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a] 189vlldm r5 190 191// UNDEF-BASELINE: error: instruction requires: armv8m.main 192// CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a] 193// CHECK-MAINLINE_DSP: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a] 194vlstm r10 195 196// New SYSm's 197 198MRS r1, MSP_NS 199// CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81] 200MSR PSP_NS, r2 201// CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88] 202MRS r3, PRIMASK_NS 203// CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83] 204MSR CONTROL_NS, r4 205// CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88] 206MRS r5, SP_NS 207// CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85] 208MRS r6,MSPLIM 209// CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86] 210MRS r7,PSPLIM 211// CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87] 212MSR MSPLIM,r8 213// CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88] 214MSR PSPLIM,r9 215// CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88] 216 217MRS r10, MSPLIM_NS 218// CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a] 219// UNDEF-BASELINE: error: invalid operand for instruction 220MSR PSPLIM_NS, r11 221// CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88] 222// UNDEF-BASELINE: error: invalid operand for instruction 223MRS r12, BASEPRI_NS 224// CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c] 225// UNDEF-BASELINE: error: invalid operand for instruction 226MRS r12, BASEPRI_MAX_NS 227// CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c] 228// UNDEF-BASELINE: error: invalid operand for instruction 229MSR FAULTMASK_NS, r14 230// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88] 231// UNDEF-BASELINE: error: invalid operand for instruction 232 233// Invalid operand tests 234// UNDEF: error: invalid operand for instruction 235// UNDEF: sg #0 236sg #0 237// UNDEF: error: invalid operand for instruction 238// UNDEF: sg r0 239sg r0 240// UNDEF: error: invalid operand for instruction 241// UNDEF: bxns r0, r1 242bxns r0, r1 243// UNDEF: error: invalid operand for instruction 244// UNDEF: blxns r0, #0 245blxns r0, #0 246// UNDEF: error: invalid operand for instruction 247// UNDEF: blxns label 248blxns label 249// UNDEF: error: invalid operand for instruction 250// UNDEF: tt r0, r1, r2 251tt r0, r1, r2 252// UNDEF: error: invalid operand for instruction 253// UNDEF: tt r0, [r1] 254tt r0, [r1] 255// UNDEF: error: invalid operand for instruction 256// UNDEF: tt r0, r1, #4 257tt r0, r1, #4 258// UNDEF: error: invalid operand for instruction 259// UNDEF: tt r0, #4 260tt r0, #4 261 262// Unpredictable operands 263// UNDEF: error: invalid operand for instruction 264// UNDEF: blxns pc 265blxns pc 266// UNDEF: error: invalid operand for instruction 267// UNDEF: tt sp, r0 268tt sp, r0 269// UNDEF: error: invalid operand for instruction 270// UNDEF: tt pc, r0 271tt pc, r0 272// UNDEF: error: invalid operand for instruction 273// UNDEF: tt r0, pc 274tt r0, pc 275 276// UNDEF: error: invalid operand for instruction 277// UNDEF: vlldm pc 278vlldm pc 279 280// UNDEF: error: invalid operand for instruction 281// UNDEF: vlstm pc 282vlstm pc 283