| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 31 cfc1 $s1,$21
131 # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
132 # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
143 # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
144 # CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
|
| /external/llvm/test/MC/Mips/ |
| D | micromips-fpu-instructions.s | 52 # CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
117 # CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
178 cfc1 $6, $0
|
| D | mips-fpu-instructions.s | 144 # CHECK: cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44]
179 cfc1 $a2,$0
|
| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext.S | 303 cfc1 v1, fcr31
384 cfc1 v1, $31
|
| /external/v8/src/compiler/mips64/ |
| D | code-generator-mips64.cc | 495 __ cfc1(kScratchReg, FCSR); \
519 __ cfc1(kScratchReg, FCSR); \
1608 __ cfc1(tmp_fcsr, FCSR); in AssembleArchInstruction() local
1616 __ cfc1(result, FCSR); in AssembleArchInstruction() local
1636 __ cfc1(tmp_fcsr, FCSR); in AssembleArchInstruction() local
1644 __ cfc1(result, FCSR); in AssembleArchInstruction() local
|
| /external/valgrind/docs/internals/ |
| D | 3_9_BUGSTATUS.txt | 120 Error: illegal operands `cfc1 $t0,$31'
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| D | valid-mips1-el.txt | 31 0x00 0xa8 0x51 0x44 # CHECK: cfc1 $17, $21
|
| D | valid-mips1.txt | 70 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 103 def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 45 cfc1 $s1,$21
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 50 cfc1 $s1,$21
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-mips32.txt | 161 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
162 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
|
| D | valid-mips32-el.txt | 59 0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| D | valid-mips2-el.txt | 38 0x00 0xa8 0x51 0x44 # CHECK: cfc1 $17, $21
|
| D | valid-mips2.txt | 108 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-mips32r5.txt | 168 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
169 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
|
| D | valid-mips32r5-el.txt | 57 0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-mips32r3.txt | 168 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
169 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
|
| D | valid-mips32r3-el.txt | 57 0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-mips32r2.txt | 171 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7
172 0x44 0x51 0xa8 0x00 # CHECK: cfc1 $17, $21
|
| D | valid-mips32r2-el.txt | 60 0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 50 cfc1 $s1,$21
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 48 cfc1 $s1,$21
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 50 cfc1 $s1,$21
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 50 cfc1 $s1,$21
|