| /external/llvm/test/MC/ARM/ |
| D | neon-bitwise-encoding.s | 169 vand d4, d7, d3
170 vand.8 d4, d7, d3
171 vand.16 d4, d7, d3
172 vand.32 d4, d7, d3
173 vand.64 d4, d7, d3
175 vand.i8 d4, d7, d3
176 vand.i16 d4, d7, d3
177 vand.i32 d4, d7, d3
178 vand.i64 d4, d7, d3
180 vand.s8 d4, d7, d3
[all …]
|
| D | neon-vld-vst-align.s | 2978 vld3.8 {d0, d2, d4}, [r4]
2979 vld3.8 {d0, d2, d4}, [r4:16]
2980 vld3.8 {d0, d2, d4}, [r4:32]
2981 vld3.8 {d0, d2, d4}, [r4:64]
2982 vld3.8 {d0, d2, d4}, [r4:128]
2983 vld3.8 {d0, d2, d4}, [r4:256]
2985 @ CHECK: vld3.8 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x0f,0x05]
2987 @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16]
2990 @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32]
2992 @ CHECK: vld3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x05]
[all …]
|
| D | neon-mul-encoding.s | 106 vmul.i16 d0, d4[2]
110 vmul.s32 d4, d3[1]
111 vmul.u32 d5, d4[0]
114 vmul.i16 q0, d4[2]
119 vmul.u32 q5, d4[0]
122 vmul.i16 d9, d0, d4[2]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
130 vmul.i16 q9, q0, d4[2]
135 vmul.u32 q4, q5, d4[0]
[all …]
|
| D | neon-vld-encoding.s | 12 vld1.16 {d4, d5, d6}, [r3:64]
15 vld1.8 {d1, d2, d3, d4}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
39 vld1.16 {d4, d5, d6}, [r3:64]!
44 vld1.16 {d4, d5, d6}, [r3:64], r6
48 vld1.8 {d1, d2, d3, d4}, [r3]!
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
53 vld1.8 {d1, d2, d3, d4}, [r3], r8
54 vld1.16 {d4, d5, d6, d7}, [r3:64], r8
67 @ CHECK: vld1.16 {d4, d5, d6}, [r3:64] @ encoding: [0x5f,0x46,0x23,0xf4]
[all …]
|
| D | thumb-fp-armv8.s | 41 vcvtp.s32.f64 s0, d4
42 @ CHECK: vcvtp.s32.f64 s0, d4 @ encoding: [0xbe,0xfe,0xc4,0x0b]
58 vcvtp.u32.f64 s0, d4
59 @ CHECK: vcvtp.u32.f64 s0, d4 @ encoding: [0xbe,0xfe,0x44,0x0b]
77 vseleq.f64 d2, d4, d8
78 @ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x04,0xfe,0x08,0x2b]
92 vminnm.f64 d4, d6, d9
93 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
115 vrinta.f64 d3, d4
116 @ CHECK: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
[all …]
|
| D | fp-armv8.s | 38 vcvtp.s32.f64 s0, d4
39 @ CHECK: vcvtp.s32.f64 s0, d4 @ encoding: [0xc4,0x0b,0xbe,0xfe]
55 vcvtp.u32.f64 s0, d4
56 @ CHECK: vcvtp.u32.f64 s0, d4 @ encoding: [0x44,0x0b,0xbe,0xfe]
74 vseleq.f64 d2, d4, d8
75 @ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x08,0x2b,0x04,0xfe]
89 vminnm.f64 d4, d6, d9
90 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe]
109 vrinta.f64 d3, d4
110 @ CHECK: vrinta.f64 d3, d4 @ encoding: [0x44,0x3b,0xb8,0xfe]
[all …]
|
| D | neon-shift-encoding.s | 382 vshl.s8 d4, d5
383 vshl.s16 d4, d5
384 vshl.s32 d4, d5
385 vshl.s64 d4, d5
387 vshl.u8 d4, d5
388 vshl.u16 d4, d5
389 vshl.u32 d4, d5
390 vshl.u64 d4, d5
402 @ CHECK: vshl.s8 d4, d4, d5 @ encoding: [0x04,0x44,0x05,0xf2]
403 @ CHECK: vshl.s16 d4, d4, d5 @ encoding: [0x04,0x44,0x15,0xf2]
[all …]
|
| D | single-precision-fp.s | 6 vsub.f64 d2, d3, d4
7 vdiv.f64 d4, d5, d6
13 @ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
23 vnmla.f64 d5, d4, d3
26 vfms.f64 d4, d5, d6
34 @ CHECK-ERRORS-NEXT: vnmla.f64 d5, d4, d3
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
58 vabs.f64 d4, d5
66 @ CHECK-ERRORS-NEXT: vabs.f64 d4, d5
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_itrans_recon_4x4_ttype1.s | 140 vmov.i16 d4[0],r8
142 vmov.i16 d4[1],r9
144 vmov.i16 d4[2],r10
146 vmov.i16 d4[3],r11
150 vmull.s16 q3,d1,d4[2] @74 * pi2_src[1]
151 vmlal.s16 q3,d0,d4[0] @74 * pi2_src[1] + 29 * pi2_src[0]
152 vmlal.s16 q3,d3,d4[1] @74 * pi2_src[1] + 29 * pi2_src[0] + 55 * pi2_src[3]
153 …vmlal.s16 q3,d2,d4[3] @pi2_out[0] = 29* pi2_src[0] + 74 * pi2_src[1] + 84* pi2_s…
155 vmull.s16 q4,d1,d4[2] @74 * pi2_src[1]
156 vmlal.s16 q4,d0,d4[1] @74 * pi2_src[1] + 55 * pi2_src[0]
[all …]
|
| D | ihevc_padding.s | 138 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
139 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
140 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
141 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
142 vst1.8 {d4,d5},[r6] @128/8 = 16 bytes store
257 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
258 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
259 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
260 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
261 vst1.8 {d4,d5},[r6] @128/8 = 16 bytes store
[all …]
|
| D | ihevc_itrans_recon_16x16.s | 230 vld1.16 d4,[r0],r6
285 vmlal.s16 q6,d4,d1[0]
287 vmlal.s16 q7,d4,d3[0]
289 vmlsl.s16 q8,d4,d3[0]
291 vmlsl.s16 q9,d4,d1[0]
310 vld1.16 d4,[r0],r6
347 vmlal.s16 q6,d4,d3[0]
355 vmlsl.s16 q7,d4,d1[0]
361 vmlal.s16 q8,d4,d1[0]
367 vmlsl.s16 q9,d4,d3[0]
[all …]
|
| D | ihevc_inter_pred_filters_luma_vert.s | 167 vld1.u8 {d4},[r3],r2 @src_tmp1 = vld1_u8(pu1_src_tmp)@
172 vmlal.u8 q4,d4,d26 @mul_res1 = vmlal_u8(mul_res1, src_tmp1, coeffabs_4)@
191 vmlal.u8 q5,d4,d25 @mul_res2 = vmlal_u8(mul_res2, src_tmp1, coeffabs_3)@
211 vmlsl.u8 q6,d4,d24
222 vmull.u8 q7,d4,d23
229 vld1.u8 {d4},[r3],r2 @src_tmp1 = vld1_u8(pu1_src_tmp)@
259 vmlal.u8 q4,d4,d26 @mul_res1 = vmlal_u8(mul_res1, src_tmp1, coeffabs_4)@
281 vmlal.u8 q5,d4,d25 @mul_res2 = vmlal_u8(mul_res2, src_tmp1, coeffabs_3)@
304 vmlsl.u8 q6,d4,d24
325 vmull.u8 q7,d4,d23
[all …]
|
| /external/valgrind/none/tests/arm/ |
| D | neon64.c | 735 TESTINSN_bin("vand d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
742 TESTINSN_bin("vbic d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
750 TESTINSN_bin("vorr d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); in main()
757 TESTINSN_bin("vorn d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); in main()
763 TESTINSN_bin("veor d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
768 TESTINSN_bin("veor d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); in main()
774 TESTINSN_bin("vbsl d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
779 TESTINSN_bin("vbsl d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); in main()
785 TESTINSN_bin("vbit d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57); in main()
790 TESTINSN_bin("vbit d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff); in main()
[all …]
|
| /external/libmpeg2/common/arm/ |
| D | icv_variance_a9.s | 84 vadd.u16 d4, d4, d5
85 vpadd.u16 d4, d4, d4
86 vpadd.u16 d4, d4, d4
106 vmov.u16 r0, d4[0]
|
| /external/libavc/common/arm/ |
| D | ih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s | 158 vext.8 d4, d0, d1, #4
161 vaddl.u8 q4, d1, d4
172 vext.8 d4, d0, d1, #4
175 vaddl.u8 q5, d1, d4
186 vext.8 d4, d0, d1, #4
189 vaddl.u8 q6, d1, d4
200 vext.8 d4, d0, d1, #4
203 vaddl.u8 q7, d1, d4
214 vext.8 d4, d0, d1, #4
217 vaddl.u8 q8, d1, d4
[all …]
|
| D | ih264_deblk_chroma_a9.s | 98 vld2.8 {d4, d5}, [r0], r1 @D4 = p0u , D5 = p0v
110 vaddl.u8 q7, d4, d2 @
174 vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r1
175 vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r0], r1
176 vld4.16 {d0[2], d2[2], d4[2], d6[2]}, [r0], r1
177 vld4.16 {d0[3], d2[3], d4[3], d6[3]}, [r0], r1
198 vaddl.u8 q9, d0, d4
213 vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r12], r1
214 vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r12], r1
215 vst4.16 {d0[2], d2[2], d4[2], d6[2]}, [r12], r1
[all …]
|
| D | ih264_intra_pred_luma_4x4_a9q.s | 414 vext.8 d4, d3, d3, #1
415 vst1.32 {d4[0]}, [r1], r3
418 vst1.16 {d4[1]}, [r1]!
419 vst1.16 {d4[2]}, [r1]
494 vext.8 d4, d3, d3, #1
496 vst1.16 {d4[1]}, [r1]!
497 vst1.16 {d4[2]}, [r1], r5
500 vst1.32 {d4[0]}, [r1], r3
572 vqrshrun.s16 d4, q10, #1
576 vst1.32 {d4[1]}, [r1], r3
[all …]
|
| /external/clang/test/SemaCXX/ |
| D | constant-expression-cxx1z.cpp | 22 constexpr D d4 = {}; variable
23 static_assert(d4.a == 10 && d4.b == 30 && d4.c == 29 && d4.q == 0 && d4.k == 0);
|
| /external/libvpx/libvpx/vp8/common/arm/neon/ |
| D | shortidct4x4llm_neon.c | 28 int16x4_t d2, d3, d4, d5, d10, d11, d12, d13; in vp8_short_idct4x4llm_neon() local
36 d4 = vld1_s16(input + 8); in vp8_short_idct4x4llm_neon()
40 q1s16 = vcombine_s16(d2, d4); // Swap d3 d4 here in vp8_short_idct4x4llm_neon()
58 d4 = vqsub_s16(d13, d10); in vp8_short_idct4x4llm_neon()
61 v2tmp0 = vtrn_s32(vreinterpret_s32_s16(d2), vreinterpret_s32_s16(d4)); in vp8_short_idct4x4llm_neon()
87 d4 = vqsub_s16(d13, d10); in vp8_short_idct4x4llm_neon()
92 d4 = vrshr_n_s16(d4, 3); in vp8_short_idct4x4llm_neon()
95 v2tmp0 = vtrn_s32(vreinterpret_s32_s16(d2), vreinterpret_s32_s16(d4)); in vp8_short_idct4x4llm_neon()
|
| /external/vixl/examples/aarch32/ |
| D | pi.cc | 44 __ Vmov(d4, 8.0); in GenerateApproximatePi()
65 __ Vadd(F64, d0, d0, d4); in GenerateApproximatePi()
66 __ Vadd(F64, d1, d1, d4); in GenerateApproximatePi()
67 __ Vadd(F64, d2, d2, d4); in GenerateApproximatePi()
68 __ Vadd(F64, d3, d3, d4); in GenerateApproximatePi()
73 __ Vmov(F64, d4, 4.0); in GenerateApproximatePi()
77 __ Vmul(F64, d0, d10, d4); in GenerateApproximatePi()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | swift-vldm.ll | 9 ; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4}
10 ; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4}
12 declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
23 %d4 = load double , double * %addr3
24 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we
25 ; don't form a "vldmia rX, {d1, d2, d3, d4}".
28 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4)
|
| /external/python/cpython2/Tools/pybench/ |
| D | Dict.py | 16 d4 = {}
22 d4 = {4:5,6:7,8:9}
28 d4 = {}
34 d4 = {4:5,6:7,8:9}
40 d4 = {}
46 d4 = {4:5,6:7,8:9}
52 d4 = {}
58 d4 = {4:5,6:7,8:9}
64 d4 = {}
70 d4 = {4:5,6:7,8:9}
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_itrans_recon_dc_chroma.s | 93 vld2.8 {d4,d5},[r7],r2
106 vaddw.u8 q14,q0,d4
116 vqmovun.s16 d4,q14
128 vst2.8 {d4,d5},[r11],r3
160 vld2.8 {d4,d5},[r0],r2
168 vaddw.u8 q14,q0,d4
175 vqmovun.s16 d4,q14
181 vzip.8 d4,d5
186 vst1.u32 {d4},[r1],r3
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | loopfilter_8_neon.asm | 45 vld1.u8 {d4}, [r2@64], r1 ; p2
62 vst1.u8 {d4}, [r2@64], r1 ; store oq1
124 vld1.u8 {d4}, [r2], r1
134 vtrn.32 d4, d16
139 vtrn.16 d4, d6
143 vtrn.8 d3, d4
164 vst2.8 {d4[0], d5[0]}, [r3], r1
165 vst2.8 {d4[1], d5[1]}, [r3], r1
166 vst2.8 {d4[2], d5[2]}, [r3], r1
167 vst2.8 {d4[3], d5[3]}, [r3], r1
[all …]
|
| /external/kernel-headers/original/uapi/linux/ |
| D | uuid.h | 31 #define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ argument
36 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
38 #define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ argument
43 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
|