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/external/llvm/test/MC/Mips/
Dmacro-ddiv.s6 ddiv $25, $11
8 # CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
19 ddiv $24,$12
21 # CHECK-NOTRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
32 ddiv $25,$0
35 ddiv $0,$9
37 # CHECK-NOTRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
48 ddiv $0,$0
51 ddiv $4,$5,$6
53 # CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
[all …]
/external/valgrind/none/tests/ppc32/
Dtest_dfp1.stdout.exp149 ddiv 2234000000000e50 / 223400000014c000 => 29f20ccf848e2a4e
150 ddiv a2340000000000e0 / 223400000014c000 => a5ed80474082c00b
151 ddiv 22240000000000cf / a21400010a395bcf => b1eeabacabd62ac3
152 ddiv 2234000000000e50 / 000400000089b000 => 7800000000000000
153 ddiv a2340000000000e0 / a21400010a395bcf => 2dfc0e4e6a205575
154 ddiv 6e4d3f1f534acdd4 / 223400000014c000 => 3e38ff87d92ca3c3
155 ddiv 6e4d3f1f534acdd4 / a2340000000000e0 => ba48c92fea1aadc6
156 ddiv 2238000000000000 / a238000000000000 => 7c00000000000000
157 ddiv 2238000000000000 / 223400000014c000 => 223c000000000000
158 ddiv 4248000000000000 / 7a34000000000000 => 0000000000000000
[all …]
/external/valgrind/none/tests/ppc64/
Dtest_dfp1.stdout.exp149 ddiv 2234000000000e50 / 223400000014c000 => 29f20ccf848e2a4e
150 ddiv a2340000000000e0 / 223400000014c000 => a5ed80474082c00b
151 ddiv 22240000000000cf / a21400010a395bcf => b1eeabacabd62ac3
152 ddiv 2234000000000e50 / 000400000089b000 => 7800000000000000
153 ddiv a2340000000000e0 / a21400010a395bcf => 2dfc0e4e6a205575
154 ddiv 6e4d3f1f534acdd4 / 223400000014c000 => 3e38ff87d92ca3c3
155 ddiv 6e4d3f1f534acdd4 / a2340000000000e0 => ba48c92fea1aadc6
156 ddiv 2238000000000000 / a238000000000000 => 7c00000000000000
157 ddiv 2238000000000000 / 223400000014c000 => 223c000000000000
158 ddiv 4248000000000000 / 7a34000000000000 => 0000000000000000
[all …]
/external/llvm/test/CodeGen/Mips/
Dmips64muldiv.ll54 ; ACC: ddiv $zero, $4, $5
56 ; GPR: ddiv $2, $4, $5
74 ; ACC: ddiv $zero, $4, $5
Dmips64instrs.ll119 ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
123 ; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
157 ; ACCMULDIV: ddiv $zero, $4, $5
Ddivrem.ll236 ; ACC64: ddiv $zero, $4, $5
239 ; GPR64: ddiv $2, $4, $5
331 ; ACC64: ddiv $zero, $4, $5
338 ; GPR64-DAG: ddiv $2, $4, $5
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dmips64instrs.ll89 ; CHECK: ddiv $zero
105 ; CHECK: ddiv $zero
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dsdiv.ll166 ; GP64-NOT-R6: ddiv $zero, $4, $5
170 ; 64R6: ddiv $2, $4, $5
175 ; MM64: ddiv $2, $4, $5
Dsrem.ll158 ; GP64-NOT-R6: ddiv $zero, $4, $5
/external/valgrind/none/tests/mips64/
Darithmetic_instruction.stdout.exp-mips648961 ddiv $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
8962 ddiv $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0x12bd6aa, LO 0x0
8963 ddiv $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
8964 ddiv $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x7e876382d2ab13, LO 0x0
8965 ddiv $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
8966 ddiv $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0xd31807e1e2825e68, LO 0xffffffff…
8967 ddiv $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
8968 ddiv $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0xb7746d775ad6a5fb, LO 0x0
8969 ddiv $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
8970 ddiv $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x42b0c0a28677b502, LO 0x0
[all …]
Darithmetic_instruction.stdout.exp-mips64r28961 ddiv $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
8962 ddiv $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0x12bd6aa, LO 0x0
8963 ddiv $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
8964 ddiv $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x7e876382d2ab13, LO 0x0
8965 ddiv $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
8966 ddiv $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0xd31807e1e2825e68, LO 0xffffffff…
8967 ddiv $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
8968 ddiv $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0xb7746d775ad6a5fb, LO 0x0
8969 ddiv $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
8970 ddiv $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x42b0c0a28677b502, LO 0x0
[all …]
/external/compiler-rt/lib/builtins/
Ddivdf3.c22 ARM_EABI_FNALIAS(ddiv, divdf3) in ARM_EABI_FNALIAS() argument
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s30 # ddiv has been re-encoded. See valid.s
Dinvalid-mips64.s51 # ddiv has been re-encoded. See valid.s
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s73 ddiv $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
74 ddiv $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
75 ddiv $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
Dvalid.s57 ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips4.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips5.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt83 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
225 0x1e 0x00 0x56 0x03 # CHECK: ddiv $zero, $26, $22
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td27 class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
127 class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
DMips64r6InstrInfo.td64 class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt89 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
246 0x1e 0x00 0x56 0x03 # CHECK: ddiv $zero, $26, $22
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMips64InstrInfo.td168 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s24 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…

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