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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMSchedule.td13 def IIC_iALUx : InstrItinClass;
14 def IIC_iALUi : InstrItinClass;
15 def IIC_iALUr : InstrItinClass;
16 def IIC_iALUsi : InstrItinClass;
17 def IIC_iALUsir : InstrItinClass;
18 def IIC_iALUsr : InstrItinClass;
19 def IIC_iBITi : InstrItinClass;
20 def IIC_iBITr : InstrItinClass;
21 def IIC_iBITsi : InstrItinClass;
22 def IIC_iBITsr : InstrItinClass;
[all …]
/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
[all …]
/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def PragmaComment : Decl;
15 def PragmaDetectMismatch : Decl;
16 def ExternCContext : Decl, DeclContext;
17 def Named : Decl<1>;
18 def Namespace : DDecl<Named>, DeclContext;
19 def UsingDirective : DDecl<Named>;
20 def NamespaceAlias : DDecl<Named>;
21 def Label : DDecl<Named>;
22 def Type : DDecl<Named, 1>;
[all …]
DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
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/external/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPURegisterInfo.td24 def R0 : SPUVecReg<0, "$lr">, DwarfRegNum<[0]>;
25 def R1 : SPUVecReg<1, "$sp">, DwarfRegNum<[1]>;
26 def R2 : SPUVecReg<2, "$2">, DwarfRegNum<[2]>;
27 def R3 : SPUVecReg<3, "$3">, DwarfRegNum<[3]>;
28 def R4 : SPUVecReg<4, "$4">, DwarfRegNum<[4]>;
29 def R5 : SPUVecReg<5, "$5">, DwarfRegNum<[5]>;
30 def R6 : SPUVecReg<6, "$6">, DwarfRegNum<[6]>;
31 def R7 : SPUVecReg<7, "$7">, DwarfRegNum<[7]>;
32 def R8 : SPUVecReg<8, "$8">, DwarfRegNum<[8]>;
33 def R9 : SPUVecReg<9, "$9">, DwarfRegNum<[9]>;
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/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
[all …]
DHexagonIntrinsicsV4.td17 def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18 def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
21 def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22 def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
25 def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26 def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
29 def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30 def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
34 def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35 def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
[all …]
DHexagonIntrinsicsV5.td13 def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
14 def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
16 def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
18 def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
19 def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
21 def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
25 def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
26 def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
29 def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
30 def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
[all …]
/external/llvm/lib/Target/AVR/
DAVR.td53 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
57 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
63 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
69 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
74 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
79 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
84 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
89 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
93 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
98 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
[all …]
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
65 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
67 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
69 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
[all …]
/external/llvm/lib/Target/Mips/
DMipsSchedule.td13 def ALU : FuncUnit;
14 def IMULDIV : FuncUnit;
20 def IIM16Alu : InstrItinClass;
21 def IIPseudo : InstrItinClass;
23 def II_ABS : InstrItinClass;
24 def II_ADDI : InstrItinClass;
25 def II_ADDIU : InstrItinClass;
26 def II_ADDIUPC : InstrItinClass;
27 def II_ADD : InstrItinClass;
28 def II_ADDU : InstrItinClass;
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/external/llvm/test/TableGen/
DNestedForeach.td14 def S#R#M#P : Droid<S, R, M, P>;
20 // CHECK: def C2D0
21 // CHECK: def C2D2
22 // CHECK: def C2D4
23 // CHECK: def C2P0
24 // CHECK: def C2P2
25 // CHECK: def C2P4
26 // CHECK: def C2Q0
27 // CHECK: def C2Q2
28 // CHECK: def C2Q4
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/external/mesa3d/src/mesa/drivers/dri/common/xmlpool/
Dt_options.h58 #define DRI_CONF_NO_RAST(def) \ argument
59 DRI_CONF_OPT_BEGIN_B(no_rast, def) \
63 #define DRI_CONF_PERFORMANCE_BOXES(def) \ argument
64 DRI_CONF_OPT_BEGIN_B(performance_boxes, def) \
68 #define DRI_CONF_ALWAYS_FLUSH_BATCH(def) \ argument
69 DRI_CONF_OPT_BEGIN_B(always_flush_batch, def) \
73 #define DRI_CONF_ALWAYS_FLUSH_CACHE(def) \ argument
74 DRI_CONF_OPT_BEGIN_B(always_flush_cache, def) \
78 #define DRI_CONF_DISABLE_THROTTLING(def) \ argument
79 DRI_CONF_OPT_BEGIN_B(disable_throttling, def) \
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.td14 def sub_fpeven : SubRegIndex;
15 def sub_fpodd : SubRegIndex;
16 def sub_32 : SubRegIndex;
74 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
75 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
76 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
77 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
78 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
79 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
80 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td14 def sub_lt : SubRegIndex;
15 def sub_gt : SubRegIndex;
16 def sub_eq : SubRegIndex;
17 def sub_un : SubRegIndex;
18 def sub_32 : SubRegIndex;
68 def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>;
69 def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>;
70 def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>;
71 def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>;
72 def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
39 def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
40 def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
43 def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
[all …]
DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
[all …]
DAArch64SchedA57.td24 def CortexA57Model : SchedMachineModel {
41 def A57UnitB : ProcResource<1>; // Type B micro-ops
42 def A57UnitI : ProcResource<2>; // Type I micro-ops
43 def A57UnitM : ProcResource<1>; // Type M micro-ops
44 def A57UnitL : ProcResource<1>; // Type L micro-ops
45 def A57UnitS : ProcResource<1>; // Type S micro-ops
46 def A57UnitX : ProcResource<1>; // Type X micro-ops
47 def A57UnitW : ProcResource<1>; // Type W micro-ops
49 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
71 def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
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/external/llvm/include/llvm/IR/
DIntrinsicsMips.td16 def mips_v2q15_ty: LLVMType<v2i16>;
17 def mips_v4q7_ty: LLVMType<v4i8>;
18 def mips_q31_ty: LLVMType<i32>;
28 def int_mips_addu_qb : GCCBuiltin<"__builtin_mips_addu_qb">,
31 def int_mips_addu_s_qb : GCCBuiltin<"__builtin_mips_addu_s_qb">,
34 def int_mips_subu_qb : GCCBuiltin<"__builtin_mips_subu_qb">,
36 def int_mips_subu_s_qb : GCCBuiltin<"__builtin_mips_subu_s_qb">,
39 def int_mips_addq_ph : GCCBuiltin<"__builtin_mips_addq_ph">,
42 def int_mips_addq_s_ph : GCCBuiltin<"__builtin_mips_addq_s_ph">,
45 def int_mips_subq_ph : GCCBuiltin<"__builtin_mips_subq_ph">,
[all …]
DIntrinsicsPowerPC.td21 def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
22 def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], []>;
23 def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
24 def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
25 def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
27 def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
29 def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
30 def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
33 def int_ppc_sync : Intrinsic<[], [], []>;
35 def int_ppc_lwsync : Intrinsic<[], [], []>;
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/external/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td16 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
17 …def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_t…
18 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
19 …def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty],…
22 def int_SI_tbuffer_store : Intrinsic <
40 def int_SI_buffer_load_dword : Intrinsic <
53 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
87 def int_SI_image_sample : SampleRaw;
88 def int_SI_image_sample_cl : SampleRaw;
89 def int_SI_image_sample_d : SampleRaw;
[all …]

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