Searched refs:divq (Results 1 – 9 of 9) sorted by relevance
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | scalar_widen_div.ll | 99 ; CHECK: divq
100 ; CHECK: divq
101 ; CHECK: divq
102 ; CHECK-NOT: divq
145 ; CHECK: divq
146 ; CHECK: divq
147 ; CHECK: divq
148 ; CHECK: divq
149 ; CHECK: divq
150 ; CHECK-NOT: divq
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| /external/llvm/test/CodeGen/X86/ |
| D | scalar_widen_div.ll | 107 ; CHECK: divq
108 ; CHECK: divq
109 ; CHECK: divq
110 ; CHECK-NOT: divq
156 ; CHECK: divq
157 ; CHECK: divq
158 ; CHECK: divq
159 ; CHECK: divq
160 ; CHECK: divq
161 ; CHECK-NOT: divq
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| D | fast-isel-divrem-x86-64.ll | 31 ; CHECK: divq
41 ; CHECK: divq
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | README.txt | 24 remq(i,j): i - (j * divq(i,j)) if j != 0
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.td | 1583 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
1587 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
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| D | X86GenAsmMatcher.inc | 3363 { X86::DIV64r, "divq", Convert__Reg1_0, { MCK_GR64 }, 0},
3364 { X86::DIV64m, "divq", Convert__Mem5_0, { MCK_Mem }, 0},
3365 { X86::DIV64r, "divq", Convert__Reg1_0, { MCK_GR64, MCK_RAX }, 0},
3366 { X86::DIV64m, "divq", Convert__Mem5_0, { MCK_Mem, MCK_RAX }, 0},
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| D | X86GenAsmWriter.inc | 3873 "decw\t\000decl\t\000decq\t\000decb\t\000divw\t\000divl\t\000divq\t\000d"
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| /external/valgrind/none/tests/amd64/ |
| D | insn_basic.def | 570 divq rdx.uq[251958251958] rax.uq[673192206673192206] : r64.uq[8765432175318642] => rax.uq[530243038…
571 divq rdx.uq[251958251958] rax.uq[673192206673192206] : m64.uq[8765432175318642] => rax.uq[530243038…
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| /external/v8/src/compiler/x64/ |
| D | code-generator-x64.cc | 1141 __ divq(i.InputRegister(1)); in AssembleArchInstruction() local
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