| /external/llvm/test/MC/Mips/ |
| D | macro-divu.s | 6 divu $25,$11
8 # CHECK-NOTRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
12 divu $24,$12
14 # CHECK-NOTRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
18 divu $25,$0
20 # CHECK-NOTRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
24 divu $0,$9
25 # CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
27 divu $0,$0
28 # CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
[all …]
|
| D | macro-divu-bad.s | 11 divu $25, $11
14 divu $25, $0
17 divu $0,$0
|
| D | micromips-alu-instructions.s | 40 # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb]
83 # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
124 divu $0, $9, $7
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | vector-arith.ll | 388 ; MIPS32: divu
389 ; MIPS32: divu
390 ; MIPS32: divu
391 ; MIPS32: divu
392 ; MIPS32: divu
393 ; MIPS32: divu
394 ; MIPS32: divu
395 ; MIPS32: divu
396 ; MIPS32: divu
397 ; MIPS32: divu
[all …]
|
| D | 8bit.pnacl.ll | 138 ; MIPS32: divu
156 ; MIPS32: divu
177 ; MIPS32: divu
196 ; MIPS32: divu
|
| D | arith.ll | 238 ; MIPS32: divu zero,{{.*}},[[REG:.*]]
261 ; MIPS32: divu zero,{{.*}},[[REG:.*]]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 40 ; NOT-R6: divu $zero, $4, $5
44 ; R6: divu $2, $4, $5
47 ; MMR3: divu $zero, $4, $5
51 ; MMR6: divu $2, $4, $5
62 ; NOT-R6: divu $zero, $4, $5
66 ; R6: divu $2, $4, $5
69 ; MMR3: divu $zero, $4, $5
73 ; MMR6: divu $2, $4, $5
84 ; NOT-R6: divu $zero, $4, $5
88 ; R6: divu $2, $4, $5
[all …]
|
| D | urem.ll | 42 ; NOT-R6: divu $zero, $[[T1]], $[[T0]]
57 ; MMR3: divu $zero, $[[T1]], $[[T0]]
80 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
88 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
101 ; MMR3: divu $zero, $[[T1]], $[[T0]]
122 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
130 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
143 ; MMR3: divu $zero, $[[T1]], $[[T0]]
162 ; NOT-R6: divu $zero, $4, $5
169 ; MMR3: divu $zero, $4, $5
|
| /external/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 88 ; ACC32: divu $zero, $4, $5
91 ; ACC64: divu $zero, $4, $5
94 ; GPR32: divu $2, $4, $5
97 ; GPR64: divu $2, $4, $5
114 ; ACC32: divu $zero, $4, $5
117 ; ACC64: divu $zero, $4, $5
182 ; ACC32: divu $zero, $4, $5
189 ; ACC64: divu $zero, $4, $5
196 ; GPR32-DAG: divu $2, $4, $5
204 ; GPR64-DAG: divu $2, $4, $5
[all …]
|
| D | assertzext-trunc.ll | 23 ; PRE-R6: divu $zero, $4, $5
28 ; R6: divu $2, $4, $5
|
| D | divu.ll | 12 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
|
| D | remu.ll | 13 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
|
| D | divu_remu.ll | 16 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | divrem.ll | 17 ; CHECK: divu $zero,
24 ; CHECK: divu $zero,
40 ; CHECK: divu $zero,
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | div1.ll | 35 define void @divu() {
36 ; CHECK-LABEL: divu:
46 ; CHECK-DAG: divu $zero, $[[J]], $[[K]]
|
| D | rem1.ll | 47 ; CHECK-DAG: divu $zero, $[[J]], $[[K]]
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips1.s | 26 # divu has been re-encoded. See valid.s
|
| D | invalid-mips2.s | 38 # divu has been re-encoded. See valid.s
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 33 # divu has been re-encoded. See valid.s
|
| D | invalid-mips1.s | 29 # divu has been re-encoded. See valid.s
|
| D | invalid-mips2.s | 41 # divu has been re-encoded. See valid.s
|
| D | invalid-mips64.s | 54 # divu has been re-encoded. See valid.s
|
| /external/valgrind/none/tests/mips64/ |
| D | arithmetic_instruction.stdout.exp-mips64 | 10223 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
10224 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
10225 divu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
10226 divu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
10227 divu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
10228 divu $t0, $t1 :: rs 0x17c56b6b, rt 0xffffffffa6322bdf, HI 0x17c56b6b, LO 0x0
10229 divu $t0, $t1 :: rs 0x1a864db2, rt 0xffffffffab710d06, HI 0x1a864db2, LO 0x0
10230 divu $t0, $t1 :: rs 0x1e475005, rt 0xffffffffafb010b1, HI 0x1e475005, LO 0x0
10231 divu $t0, $t1 :: rs 0x2608edb8, rt 0xffffffff97ffad0c, HI 0x2608edb8, LO 0x0
10232 divu $t0, $t1 :: rs 0x22c9f00f, rt 0xffffffff933eb0bb, HI 0x22c9f00f, LO 0x0
[all …]
|
| D | arithmetic_instruction.stdout.exp-mips64r2 | 10223 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
10224 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
10225 divu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
10226 divu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
10227 divu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
10228 divu $t0, $t1 :: rs 0x17c56b6b, rt 0xffffffffa6322bdf, HI 0x17c56b6b, LO 0x0
10229 divu $t0, $t1 :: rs 0x1a864db2, rt 0xffffffffab710d06, HI 0x1a864db2, LO 0x0
10230 divu $t0, $t1 :: rs 0x1e475005, rt 0xffffffffafb010b1, HI 0x1e475005, LO 0x0
10231 divu $t0, $t1 :: rs 0x2608edb8, rt 0xffffffff97ffad0c, HI 0x2608edb8, LO 0x0
10232 divu $t0, $t1 :: rs 0x22c9f00f, rt 0xffffffff933eb0bb, HI 0x22c9f00f, LO 0x0
[all …]
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 42 divu $zero,$25,$15
|