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Searched refs:dmfc1 (Results 1 – 25 of 42) sorted by relevance

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/external/valgrind/none/tests/mips64/
Dmove_instructions.stdout.exp-LE2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b502
[all …]
Dmove_instructions.stdout.exp-BE2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b502
[all …]
Dchange_fp_mode.stdout.exp24 dmfc1 $t0, $f0 :: t0: 1234567890abcdef
25 dmfc1 $t0, $f1 :: t0: 5a5a
73 dmfc1 $t0, $f0 :: t0: 1234567890abcdef
74 dmfc1 $t0, $f1 :: t0: 1234567890abcdef
122 dmfc1 $t0, $f0 :: t0: 1234567890abcdef
123 dmfc1 $t0, $f1 :: t0: 5a5a
/external/llvm/test/CodeGen/Mips/
Dfpxx.ll208 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
211 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
215 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
218 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
Dmips64-libcall.ll9 ; HARD-NOT: dmfc1 $4
Dfcopysign-f32-f64.ll45 ; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}}
/external/v8/src/mips64/
Dmacro-assembler-mips64.cc1500 dmfc1(scratch, fd); in Usdc1()
1863 dmfc1(scratch1, fs); in Neg_d()
1894 dmfc1(t8, fs); in Cvt_d_ul()
1945 dmfc1(t8, fs); in Cvt_s_ul()
2002 dmfc1(t8, fs); in Trunc_l_ud()
2145 dmfc1(rs, scratch); in Trunc_ul_d()
2152 dmfc1(rs, scratch); in Trunc_ul_d()
2159 dmfc1(result, scratch); in Trunc_ul_d()
2193 dmfc1(rs, scratch); in Trunc_ul_s()
2200 dmfc1(rs, scratch); in Trunc_ul_s()
[all …]
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s22 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
Dinvalid-mips4.s22 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
Dinvalid-mips5.s22 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt86 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
227 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
Dvalid-mips64.txt207 0x44 0x22 0x70 0x00 # CHECK: dmfc1 $2, $f14
208 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td38 class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
163 class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt92 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
248 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
Dvalid-mips64r2.txt225 0x44 0x22 0x70 0x00 # CHECK: dmfc1 $2, $f14
226 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s207 dmfc1 $9, $f4 # CHECK: dmfc1 $9, $f4 # encoding: [0x55,0x24,0x24,0x3b]
/external/v8/src/compiler/mips64/
Dcode-generator-mips64.cc510 __ dmfc1(at, i.OutputDoubleRegister()); \
1614 __ dmfc1(i.OutputRegister(), scratch); in AssembleArchInstruction() local
1642 __ dmfc1(i.OutputRegister(0), scratch); in AssembleArchInstruction() local
1689 __ dmfc1(i.OutputRegister(), i.InputDoubleRegister(0)); in AssembleArchInstruction() local
2295 __ dmfc1(result, kDoubleCompareReg); in AssembleArchBoolean() local
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips3.s26 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips4.s24 …dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
Dinvalid-mips5.s24 …dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/llvm/test/MC/Mips/mips3/
Dvalid.s76 dmfc1 $12,$f13
/external/llvm/test/MC/Disassembler/Mips/mips3/
Dvalid-mips3-el.txt69 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
/external/llvm/test/MC/Mips/mips5/
Dvalid.s80 dmfc1 $12,$f13
/external/llvm/test/MC/Mips/mips4/
Dvalid.s80 dmfc1 $12,$f13
/external/llvm/test/MC/Mips/mips64/
Dvalid.s86 dmfc1 $12,$f13

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